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msm: camera: isp: Add decode format1 support for v780

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Decode format1 is required for payload decoding in
multi VCDT usecase.Format type is packed in 8 bits.

We will get 8 bits value as format type from UMD to
get decode format1.

CRs-Fixed: 2948116
Change-Id: I81bc816c1fc53ff8949d8920d076461ff1895e45
Signed-off-by: Chandan Kumar Jha <cjha@codeaurora.org>
This commit is contained in:
Chandan Kumar Jha
2021-06-17 23:47:16 +05:30
parent 8b5f97b80f
commit cf99d6942b
12 changed files with 193 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c
View File

@@ -957,7 +957,7 @@ static int cam_custom_hw_mgr_acquire_get_unified_dev_str(
port_info->vc[0] = in->vc[0]; port_info->vc[0] = in->vc[0];
port_info->dt[0] = in->dt[0]; port_info->dt[0] = in->dt[0];
port_info->num_valid_vc_dt = in->num_valid_vc_dt; port_info->num_valid_vc_dt = in->num_valid_vc_dt;
port_info->format = in->format; port_info->format[0] = in->format;
port_info->test_pattern = in->test_pattern; port_info->test_pattern = in->test_pattern;
port_info->usage_type = in->usage_type; port_info->usage_type = in->usage_type;
port_info->left_start = in->left_start; port_info->left_start = in->left_start;

10
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
View File

@@ -4456,7 +4456,7 @@ static int cam_ife_mgr_acquire_get_unified_structure_v0(
in_port->vc[0] = in->vc; in_port->vc[0] = in->vc;
in_port->dt[0] = in->dt; in_port->dt[0] = in->dt;
in_port->num_valid_vc_dt = 1; in_port->num_valid_vc_dt = 1;
in_port->format = in->format; in_port->format[0] = in->format;
in_port->test_pattern = in->test_pattern; in_port->test_pattern = in->test_pattern;
in_port->usage_type = in->usage_type; in_port->usage_type = in->usage_type;
in_port->left_start = in->left_start; in_port->left_start = in->left_start;
@@ -4580,7 +4580,11 @@ static int cam_ife_mgr_acquire_get_unified_structure_v2(
in_port->dt[i] = in->dt[i]; in_port->dt[i] = in->dt[i];
} }
in_port->format = in->format; for (i = 0; i < in_port->num_valid_vc_dt; i++) {
in_port->format[i] = (in->format >> (i * CAM_IFE_DECODE_FORMAT_SHIFT_VAL)) &
CAM_IFE_DECODE_FORMAT_MASK;
}
in_port->test_pattern = in->test_pattern; in_port->test_pattern = in->test_pattern;
in_port->usage_type = in->usage_type; in_port->usage_type = in->usage_type;
in_port->left_start = in->left_start; in_port->left_start = in->left_start;
@@ -4935,7 +4939,7 @@ void cam_ife_mgr_acquire_get_unified_dev_str(struct cam_isp_in_port_info *in,
gen_port_info->vc[0] = in->vc; gen_port_info->vc[0] = in->vc;
gen_port_info->dt[0] = in->dt; gen_port_info->dt[0] = in->dt;
gen_port_info->num_valid_vc_dt = 1; gen_port_info->num_valid_vc_dt = 1;
gen_port_info->format = in->format; gen_port_info->format[0] = in->format;
gen_port_info->test_pattern = in->test_pattern; gen_port_info->test_pattern = in->test_pattern;
gen_port_info->usage_type = in->usage_type; gen_port_info->usage_type = in->usage_type;
gen_port_info->left_start = in->left_start; gen_port_info->left_start = in->left_start;

1
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h
View File

@@ -1105,6 +1105,7 @@ static struct cam_ife_csid_ver2_common_reg_info
.dt_shift_val = 16, .dt_shift_val = 16,
.crop_shift_val = 16, .crop_shift_val = 16,
.decode_format_shift_val = 12, .decode_format_shift_val = 12,
.decode_format1_supported = false,
.frame_id_decode_en_shift_val = 1, .frame_id_decode_en_shift_val = 1,
.multi_vcdt_vc1_shift_val = 2, .multi_vcdt_vc1_shift_val = 2,
.multi_vcdt_dt1_shift_val = 7, .multi_vcdt_dt1_shift_val = 7,

3
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h
View File

@@ -1130,6 +1130,8 @@ static struct cam_ife_csid_ver2_common_reg_info
.dt_shift_val = 16, .dt_shift_val = 16,
.crop_shift_val = 16, .crop_shift_val = 16,
.decode_format_shift_val = 12, .decode_format_shift_val = 12,
.decode_format1_shift_val = 16,
.decode_format1_supported = true,
.frame_id_decode_en_shift_val = 1, .frame_id_decode_en_shift_val = 1,
.multi_vcdt_vc1_shift_val = 2, .multi_vcdt_vc1_shift_val = 2,
.multi_vcdt_dt1_shift_val = 7, .multi_vcdt_dt1_shift_val = 7,
@@ -1176,6 +1178,7 @@ static struct cam_ife_csid_ver2_common_reg_info
.format_measure_width_mask_val = 0xFFFF, .format_measure_width_mask_val = 0xFFFF,
.format_measure_width_shift_val = 0x0, .format_measure_width_shift_val = 0x0,
.top_buf_done_irq_mask = 0x2000, .top_buf_done_irq_mask = 0x2000,
.decode_format_payload_only = 0xF,
}; };
static struct cam_ife_csid_ver2_top_reg_info static struct cam_ife_csid_ver2_top_reg_info

6
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c
View File

@@ -516,9 +516,11 @@ int cam_ife_csid_check_in_port_args(
if ((reserve->res_id == CAM_IFE_PIX_PATH_RES_IPP || if ((reserve->res_id == CAM_IFE_PIX_PATH_RES_IPP ||
reserve->res_id == CAM_IFE_PIX_PATH_RES_PPP) && reserve->res_id == CAM_IFE_PIX_PATH_RES_PPP) &&
(cam_ife_csid_is_pix_res_format_supported( (cam_ife_csid_is_pix_res_format_supported(
reserve->in_port->format))) { reserve->in_port->format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0]))) {
CAM_ERR(CAM_ISP, "CSID %d, res_id %d, unsupported format %d", CAM_ERR(CAM_ISP, "CSID %d, res_id %d, unsupported format %d",
hw_idx, reserve->res_id, reserve->in_port->format); hw_idx,
reserve->res_id,
reserve->in_port->format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0]);
return -EINVAL; return -EINVAL;
} }

4
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c
View File

@@ -1093,7 +1093,7 @@ static int cam_ife_csid_hw_ver1_path_cfg(
{ {
path_cfg->cid = cid; path_cfg->cid = cid;
path_cfg->in_format = reserve->in_port->format; path_cfg->in_format = reserve->in_port->format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0];
path_cfg->out_format = reserve->out_port->format; path_cfg->out_format = reserve->out_port->format;
path_cfg->sync_mode = reserve->sync_mode; path_cfg->sync_mode = reserve->sync_mode;
path_cfg->height = reserve->in_port->height; path_cfg->height = reserve->in_port->height;
@@ -1237,7 +1237,7 @@ static int cam_ife_csid_ver1_tpg_config(
return -EINVAL; return -EINVAL;
} }
switch (reserve->in_port->format) { switch (reserve->in_port->format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0]) {
case CAM_FORMAT_MIPI_RAW_8: case CAM_FORMAT_MIPI_RAW_8:
csid_hw->tpg_cfg.encode_format = CAM_IFE_CSID_TPG_ENCODE_RAW8; csid_hw->tpg_cfg.encode_format = CAM_IFE_CSID_TPG_ENCODE_RAW8;
break; break;

172
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c
View File

@@ -1817,15 +1817,83 @@ static int cam_ife_csid_ver2_disable_path(
return rc; return rc;
} }
static int cam_ife_csid_ver2_decode_format1_validate(
struct cam_ife_csid_ver2_hw *csid_hw,
struct cam_isp_resource_node *res)
{
int rc = 0;
const struct cam_ife_csid_ver2_reg_info *csid_reg =
(struct cam_ife_csid_ver2_reg_info *)csid_hw->core_info->csid_reg;
struct cam_ife_csid_ver2_path_cfg *path_cfg =
(struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
struct cam_ife_csid_cid_data *cid_data = &csid_hw->cid_data[path_cfg->cid];
/* Validation is only required for multi vc dt use case */
if (!cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid)
return rc;
if ((path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt ==
csid_reg->cmn_reg->decode_format_payload_only) ||
(path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt ==
csid_reg->cmn_reg->decode_format_payload_only)) {
if (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt !=
path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt) {
CAM_ERR(CAM_ISP,
"CSID:%d decode_fmt %d decode_fmt1 %d mismatch",
csid_hw->hw_intf->hw_idx,
path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt,
path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt);
rc = -EINVAL;
goto err;
}
}
if ((cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].vc ==
cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].vc) &&
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt ==
cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt)) {
if (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt !=
path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt) {
CAM_ERR(CAM_ISP,
"CSID:%d Wrong multi VC-DT configuration",
csid_hw->hw_intf->hw_idx);
CAM_ERR(CAM_ISP,
"fmt %d fmt1 %d vc %d vc1 %d dt %d dt1 %d",
path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt,
path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt,
cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].vc,
cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].vc,
cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt,
cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt);
rc = -EINVAL;
goto err;
}
}
return rc;
err:
CAM_ERR(CAM_ISP, "Invalid decode fmt1 cfg csid[%d] res [id %d name %s] rc %d",
csid_hw->hw_intf->hw_idx, res->res_id, res->res_name, rc);
return rc;
}
static int cam_ife_csid_hw_ver2_config_path_data( static int cam_ife_csid_hw_ver2_config_path_data(
struct cam_ife_csid_ver2_hw *csid_hw, struct cam_ife_csid_ver2_hw *csid_hw,
struct cam_ife_csid_ver2_path_cfg *path_cfg, struct cam_ife_csid_ver2_path_cfg *path_cfg,
struct cam_csid_hw_reserve_resource_args *reserve, struct cam_csid_hw_reserve_resource_args *reserve,
uint32_t cid) uint32_t cid)
{ {
int rc = 0, i = 0;
bool is_rpp = false;
const struct cam_ife_csid_ver2_reg_info *csid_reg =
(struct cam_ife_csid_ver2_reg_info *)csid_hw->core_info->csid_reg;
struct cam_ife_csid_cid_data *cid_data = &csid_hw->cid_data[cid];
struct cam_isp_resource_node *res = &csid_hw->path_res[reserve->res_id];
for(i = 0; i < reserve->in_port->num_valid_vc_dt; i++)
path_cfg->in_format[i] = reserve->in_port->format[i];
path_cfg->cid = cid; path_cfg->cid = cid;
path_cfg->in_format = reserve->in_port->format;
path_cfg->out_format = reserve->out_port->format; path_cfg->out_format = reserve->out_port->format;
path_cfg->sync_mode = reserve->sync_mode; path_cfg->sync_mode = reserve->sync_mode;
path_cfg->height = reserve->in_port->height; path_cfg->height = reserve->in_port->height;
@@ -1883,7 +1951,70 @@ static int cam_ife_csid_hw_ver2_config_path_data(
reserve->in_port->left_start, reserve->in_port->left_start,
reserve->in_port->left_stop); reserve->in_port->left_stop);
} }
return 0;
switch (reserve->res_id) {
case CAM_IFE_PIX_PATH_RES_RDI_0:
case CAM_IFE_PIX_PATH_RES_RDI_1:
case CAM_IFE_PIX_PATH_RES_RDI_2:
case CAM_IFE_PIX_PATH_RES_RDI_3:
case CAM_IFE_PIX_PATH_RES_RDI_4:
is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
rc = cam_ife_csid_get_format_rdi(
path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
path_cfg->out_format,
&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
is_rpp);
if (rc)
goto end;
if (csid_reg->cmn_reg->decode_format1_supported &&
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid)) {
rc = cam_ife_csid_get_format_rdi(
path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
path_cfg->out_format,
&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
is_rpp);
if (rc)
goto end;
}
break;
case CAM_IFE_PIX_PATH_RES_IPP:
case CAM_IFE_PIX_PATH_RES_PPP:
rc = cam_ife_csid_get_format_ipp_ppp(
path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0]);
if (rc)
goto end;
if (csid_reg->cmn_reg->decode_format1_supported &&
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid)) {
rc = cam_ife_csid_get_format_ipp_ppp(
path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1]);
if (rc)
goto end;
}
break;
default:
rc = -EINVAL;
CAM_ERR(CAM_ISP, "Invalid Res id %u", reserve->res_id);
break;
}
if (csid_reg->cmn_reg->decode_format1_supported &&
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid)) {
rc = cam_ife_csid_ver2_decode_format1_validate(csid_hw, res);
if (rc) {
CAM_ERR(CAM_ISP, "CSID[%d] res %d decode fmt1 validation failed",
csid_hw->hw_intf->hw_idx, res);
goto end;
}
}
end:
return rc;
} }
static int cam_ife_csid_hw_ver2_config_rx( static int cam_ife_csid_hw_ver2_config_rx(
@@ -2314,8 +2445,6 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
uint32_t val; uint32_t val;
struct cam_ife_csid_ver2_path_cfg *path_cfg; struct cam_ife_csid_ver2_path_cfg *path_cfg;
struct cam_ife_csid_cid_data *cid_data; struct cam_ife_csid_cid_data *cid_data;
struct cam_ife_csid_path_format path_format = {0};
bool is_rpp = false;
void __iomem *mem_base; void __iomem *mem_base;
soc_info = &csid_hw->hw_info->soc_info; soc_info = &csid_hw->hw_info->soc_info;
@@ -2345,12 +2474,6 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
return 0; return 0;
} }
is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
rc = cam_ife_csid_get_format_rdi(path_cfg->in_format,
path_cfg->out_format, &path_format, is_rpp);
if (rc)
return rc;
/*Configure cfg0: /*Configure cfg0:
* VC * VC
* DT * DT
@@ -2365,7 +2488,8 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt << (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt <<
cmn_reg->dt_shift_val) | cmn_reg->dt_shift_val) |
(path_cfg->cid << cmn_reg->dt_id_shift_val) | (path_cfg->cid << cmn_reg->dt_id_shift_val) |
(path_format.decode_fmt << cmn_reg->decode_format_shift_val); (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt <<
cmn_reg->decode_format_shift_val);
if (csid_reg->cmn_reg->vfr_supported) if (csid_reg->cmn_reg->vfr_supported)
val |= path_cfg->vfr_en << cmn_reg->vfr_en_shift_val; val |= path_cfg->vfr_en << cmn_reg->vfr_en_shift_val;
@@ -2383,6 +2507,11 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt << (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt <<
cmn_reg->multi_vcdt_dt1_shift_val) | cmn_reg->multi_vcdt_dt1_shift_val) |
(1 << cmn_reg->multi_vcdt_en_shift_val); (1 << cmn_reg->multi_vcdt_en_shift_val);
if (csid_reg->cmn_reg->decode_format1_supported)
val |= (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt <<
csid_reg->cmn_reg->decode_format1_shift_val);
cam_io_w_mb(val, mem_base + path_reg->multi_vcdt_cfg0_addr); cam_io_w_mb(val, mem_base + path_reg->multi_vcdt_cfg0_addr);
} }
@@ -2407,10 +2536,11 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
cmn_reg->timestamp_stb_sel_shift_val); cmn_reg->timestamp_stb_sel_shift_val);
if (path_reg->mipi_pack_supported) if (path_reg->mipi_pack_supported)
val |= path_format.packing_fmt << val |= path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].packing_fmt <<
path_reg->packing_fmt_shift_val; path_reg->packing_fmt_shift_val;
val |= path_format.plain_fmt << path_reg->plain_fmt_shift_val; val |= (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].plain_fmt <<
path_reg->plain_fmt_shift_val);
if (csid_hw->debug_info.debug_val & if (csid_hw->debug_info.debug_val &
CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO) CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO)
@@ -2470,7 +2600,6 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
uint32_t val = 0; uint32_t val = 0;
struct cam_ife_csid_ver2_path_cfg *path_cfg; struct cam_ife_csid_ver2_path_cfg *path_cfg;
struct cam_ife_csid_cid_data *cid_data; struct cam_ife_csid_cid_data *cid_data;
struct cam_ife_csid_path_format path_format = {0};
void __iomem *mem_base; void __iomem *mem_base;
soc_info = &csid_hw->hw_info->soc_info; soc_info = &csid_hw->hw_info->soc_info;
@@ -2491,9 +2620,6 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
cid_data = &csid_hw->cid_data[path_cfg->cid]; cid_data = &csid_hw->cid_data[path_cfg->cid];
mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base; mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
rc = cam_ife_csid_get_format_ipp_ppp(path_cfg->in_format,
&path_format);
/*Configure: /*Configure:
* VC * VC
* DT * DT
@@ -2507,7 +2633,8 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt << (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].dt <<
cmn_reg->dt_shift_val) | cmn_reg->dt_shift_val) |
(path_cfg->cid << cmn_reg->dt_id_shift_val) | (path_cfg->cid << cmn_reg->dt_id_shift_val) |
(path_format.decode_fmt << cmn_reg->decode_format_shift_val); (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].decode_fmt <<
cmn_reg->decode_format_shift_val);
if (csid_reg->cmn_reg->vfr_supported) if (csid_reg->cmn_reg->vfr_supported)
val |= path_cfg->vfr_en << cmn_reg->vfr_en_shift_val; val |= path_cfg->vfr_en << cmn_reg->vfr_en_shift_val;
@@ -2529,6 +2656,11 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
(cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt << (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].dt <<
cmn_reg->multi_vcdt_dt1_shift_val) | cmn_reg->multi_vcdt_dt1_shift_val) |
(1 << cmn_reg->multi_vcdt_en_shift_val); (1 << cmn_reg->multi_vcdt_en_shift_val);
if(csid_reg->cmn_reg->decode_format1_supported)
val |= (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].decode_fmt <<
csid_reg->cmn_reg->decode_format1_shift_val);
cam_io_w_mb(val, mem_base + path_reg->multi_vcdt_cfg0_addr); cam_io_w_mb(val, mem_base + path_reg->multi_vcdt_cfg0_addr);
} }
@@ -4086,7 +4218,9 @@ static int cam_ife_csid_ver2_reg_update(
for (i = 0; i < rup_args->num_res; i++) { for (i = 0; i < rup_args->num_res; i++) {
path_reg = csid_reg->path_reg[rup_args->res[i]->res_id]; path_reg = csid_reg->path_reg[rup_args->res[i]->res_id];
if (!path_reg) { if (!path_reg) {
CAM_ERR(CAM_ISP, "Invalid Path Resource"); CAM_ERR(CAM_ISP, "Invalid Path Resource [id %d name %s]",
rup_args->res[i]->res_id,
rup_args->res[i]->res_name);
rc = -EINVAL; rc = -EINVAL;
goto err; goto err;
} }

10
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h
View File

@@ -131,7 +131,9 @@ struct cam_ife_csid_ver2_camif_data {
* @camif_data: CAMIF data * @camif_data: CAMIF data
* @error_ts: Error timestamp * @error_ts: Error timestamp
* @cid: cid value for path * @cid: cid value for path
* @in_format: input format * @path_format: Array of Path format which contains format
* info i.e Decode format, Packing format etc
* @in_format: Array of input format which contains format type
* @out_format: output format * @out_format: output format
* @start_pixel: start pixel for horizontal crop * @start_pixel: start pixel for horizontal crop
* @end_pixel: end pixel for horizontal crop * @end_pixel: end pixel for horizontal crop
@@ -169,8 +171,9 @@ struct cam_ife_csid_ver2_camif_data {
struct cam_ife_csid_ver2_path_cfg { struct cam_ife_csid_ver2_path_cfg {
struct cam_ife_csid_ver2_camif_data camif_data; struct cam_ife_csid_ver2_camif_data camif_data;
struct timespec64 error_ts; struct timespec64 error_ts;
struct cam_ife_csid_path_format path_format[CAM_ISP_VC_DT_CFG];
uint32_t cid; uint32_t cid;
uint32_t in_format; uint32_t in_format[CAM_ISP_VC_DT_CFG];
uint32_t out_format; uint32_t out_format;
uint32_t start_pixel; uint32_t start_pixel;
uint32_t end_pixel; uint32_t end_pixel;
@@ -373,6 +376,8 @@ struct cam_ife_csid_ver2_common_reg_info {
uint32_t frame_id_decode_en_shift_val; uint32_t frame_id_decode_en_shift_val;
uint32_t vfr_en_shift_val; uint32_t vfr_en_shift_val;
uint32_t decode_format_shift_val; uint32_t decode_format_shift_val;
uint32_t decode_format1_shift_val;
bool decode_format1_supported;
uint32_t start_mode_shift_val; uint32_t start_mode_shift_val;
uint32_t start_cmd_shift_val; uint32_t start_cmd_shift_val;
uint32_t path_en_shift_val; uint32_t path_en_shift_val;
@@ -469,6 +474,7 @@ struct cam_ife_csid_ver2_common_reg_info {
uint32_t top_reset_irq_mask; uint32_t top_reset_irq_mask;
uint32_t top_buf_done_irq_mask; uint32_t top_buf_done_irq_mask;
uint32_t epoch_div_factor; uint32_t epoch_div_factor;
uint32_t decode_format_payload_only;
}; };
struct cam_ife_csid_ver2_reg_info { struct cam_ife_csid_ver2_reg_info {

1
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h
View File

@@ -338,6 +338,7 @@ static struct cam_ife_csid_ver2_common_reg_info
.dt_shift_val = 16, .dt_shift_val = 16,
.crop_shift_val = 16, .crop_shift_val = 16,
.decode_format_shift_val = 12, .decode_format_shift_val = 12,
.decode_format1_supported = false,
.frame_id_decode_en_shift_val = 1, .frame_id_decode_en_shift_val = 1,
.multi_vcdt_vc1_shift_val = 2, .multi_vcdt_vc1_shift_val = 2,
.multi_vcdt_dt1_shift_val = 7, .multi_vcdt_dt1_shift_val = 7,

3
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite780.h
View File

@@ -367,6 +367,8 @@ static struct cam_ife_csid_ver2_common_reg_info
.dt_shift_val = 16, .dt_shift_val = 16,
.crop_shift_val = 16, .crop_shift_val = 16,
.decode_format_shift_val = 12, .decode_format_shift_val = 12,
.decode_format1_shift_val = 16,
.decode_format1_supported = true,
.frame_id_decode_en_shift_val = 1, .frame_id_decode_en_shift_val = 1,
.multi_vcdt_vc1_shift_val = 2, .multi_vcdt_vc1_shift_val = 2,
.multi_vcdt_dt1_shift_val = 7, .multi_vcdt_dt1_shift_val = 7,
@@ -400,6 +402,7 @@ static struct cam_ife_csid_ver2_common_reg_info
.only_master_rup = 1, .only_master_rup = 1,
.top_reset_irq_mask = 0x1, .top_reset_irq_mask = 0x1,
.top_buf_done_irq_mask = 0x2000, .top_buf_done_irq_mask = 0x2000,
.decode_format_payload_only = 0xF,
}; };
static struct cam_ife_csid_csi2_rx_reg_info static struct cam_ife_csid_csi2_rx_reg_info

2
drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h
View File

@@ -100,7 +100,7 @@ struct cam_isp_in_port_generic_info {
uint32_t vc[CAM_ISP_VC_DT_CFG]; uint32_t vc[CAM_ISP_VC_DT_CFG];
uint32_t dt[CAM_ISP_VC_DT_CFG]; uint32_t dt[CAM_ISP_VC_DT_CFG];
uint32_t num_valid_vc_dt; uint32_t num_valid_vc_dt;
uint32_t format; uint32_t format[CAM_ISP_VC_DT_CFG];
uint32_t test_pattern; uint32_t test_pattern;
uint32_t usage_type; uint32_t usage_type;
uint32_t left_start; uint32_t left_start;

9
include/uapi/camera/media/cam_isp.h
View File

@@ -183,6 +183,15 @@
#define CAM_ISP_PARAM_CORE_CFG_HDR_MUX_SEL BIT(0) #define CAM_ISP_PARAM_CORE_CFG_HDR_MUX_SEL BIT(0)
#define CAM_ISP_PARAM_CORE_CFG_PP_FORMAT BIT(16) #define CAM_ISP_PARAM_CORE_CFG_PP_FORMAT BIT(16)
/**
* Decode format1 Support for multi VCDT use case.
* Format type is packed in 8 bits. BIT(0-7) is
* format and BIT(8-15) is format1 type in the format
* variable
*/
#define CAM_IFE_DECODE_FORMAT_MASK 0xFF
#define CAM_IFE_DECODE_FORMAT_SHIFT_VAL 8
/* Query devices */ /* Query devices */
/** /**
* struct cam_isp_dev_cap_info - A cap info for particular hw type * struct cam_isp_dev_cap_info - A cap info for particular hw type