disp: msm: sde: add support for AVR_STEP feature

Add AVR step support so SW can trigger a late frame and instead
of immediately triggering, HW will perform the update at the
start of the next step interval. This allows for a fixed SW
vsync timeline to be maintained in userland, eliminating the
usual drift from the actual HW vsync caused by a late frame.

This change adds AVR_STEP support via a DRM property.

Change-Id: I4cf8a296989805f134c2165a3bed0b050bb09c96
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This commit is contained in:
Steve Cohen
2021-01-19 19:27:57 -05:00
父節點 ccf41a547c
當前提交 cf86c94f8e
共有 9 個文件被更改,包括 146 次插入83 次删除

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@@ -367,21 +367,20 @@ static void _sde_encoder_phys_vid_setup_avr(
static void _sde_encoder_phys_vid_avr_ctrl(struct sde_encoder_phys *phys_enc)
{
struct intf_avr_params avr_params;
struct sde_encoder_phys_vid *vid_enc =
to_sde_encoder_phys_vid(phys_enc);
struct sde_encoder_phys_vid *vid_enc = to_sde_encoder_phys_vid(phys_enc);
u32 avr_step_fps = sde_connector_get_avr_step(phys_enc->connector);
avr_params.avr_mode = sde_connector_get_qsync_mode(
phys_enc->connector);
memset(&avr_params, 0, sizeof(avr_params));
avr_params.avr_mode = sde_connector_get_qsync_mode(phys_enc->connector);
if (avr_step_fps)
avr_params.avr_step_lines = mult_frac(phys_enc->cached_mode.vtotal,
vid_enc->timing_params.vrefresh, avr_step_fps);
if (vid_enc->base.hw_intf->ops.avr_ctrl) {
vid_enc->base.hw_intf->ops.avr_ctrl(
vid_enc->base.hw_intf,
&avr_params);
}
if (vid_enc->base.hw_intf->ops.avr_ctrl)
vid_enc->base.hw_intf->ops.avr_ctrl(vid_enc->base.hw_intf, &avr_params);
SDE_EVT32(DRMID(phys_enc->parent),
phys_enc->hw_intf->idx - INTF_0,
avr_params.avr_mode);
SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0,
avr_params.avr_mode, avr_params.avr_step_lines, avr_step_fps);
}
static void sde_encoder_phys_vid_setup_timing_engine(