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disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"

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As per HW recommendation, FAL10_VETO_OVERRIDE register can
be programmed to disable FAL10 in alternate to disabling
uidle at the sspp level as disabling UIDLE controller will
only disable DPU traffic shaping and will not stop the
system from entering FAL10 state. This change programs
FAL10_VETO_OVERRIDE register during uidle disable and also
sets CTL_x_UIDLE_ACTIVE register to always one to avoid
race condition between different CTL paths.

Change-Id: I9c55f5da2037cb8c448cc978eac0a04608a93650
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This commit is contained in:
Yashwanth
2022-01-03 15:37:12 +05:30
parent 17970cc74c
commit cf0f2627c4
3 changed files with 9 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
msm/sde/sde_crtc.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat * Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com> * Author: Rob Clark <robdclark@gmail.com>
@@ -3607,13 +3607,8 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
_sde_crtc_dest_scaler_setup(crtc); _sde_crtc_dest_scaler_setup(crtc);
sde_cp_crtc_apply_noise(crtc, old_state); sde_cp_crtc_apply_noise(crtc, old_state);
if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty) { if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)
sde_core_perf_crtc_update_uidle(crtc, true); sde_core_perf_crtc_update_uidle(crtc, true);
} else if (!test_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask) &&
!sde_kms->perf.uidle_enabled)
sde_core_perf_uidle_setup_ctl(crtc, false);
test_and_clear_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);
/* update cached_encoder_mask if new conn is added or removed */ /* update cached_encoder_mask if new conn is added or removed */
if (crtc->state->connectors_changed) if (crtc->state->connectors_changed)
@@ -4301,7 +4296,6 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc)
/* mark other properties which need to be dirty for next update */ /* mark other properties which need to be dirty for next update */
set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask); set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask);
set_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);
if (cstate->num_ds_enabled) if (cstate->num_ds_enabled)
set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty); set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
} }

3
msm/sde/sde_crtc.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat * Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com> * Author: Rob Clark <robdclark@gmail.com>
@@ -443,7 +443,6 @@ enum sde_crtc_dirty_flags {
SDE_CRTC_DIRTY_DEST_SCALER, SDE_CRTC_DIRTY_DEST_SCALER,
SDE_CRTC_DIRTY_DIM_LAYERS, SDE_CRTC_DIRTY_DIM_LAYERS,
SDE_CRTC_NOISE_LAYER, SDE_CRTC_NOISE_LAYER,
SDE_CRTC_DIRTY_UIDLE,
SDE_CRTC_DIRTY_MAX, SDE_CRTC_DIRTY_MAX,
}; };

7
msm/sde/sde_hw_uidle.c
View File

@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* *
*/ */
@@ -162,7 +163,7 @@ void sde_hw_uidle_setup_ctl(struct sde_hw_uidle *uidle,
{ {
struct sde_hw_blk_reg_map *c = &uidle->hw; struct sde_hw_blk_reg_map *c = &uidle->hw;
bool enable = false; bool enable = false;
u32 reg_val; u32 reg_val, fal10_veto_regval = 0;
reg_val = SDE_REG_READ(c, UIDLE_CTL); reg_val = SDE_REG_READ(c, UIDLE_CTL);
@@ -183,6 +184,10 @@ void sde_hw_uidle_setup_ctl(struct sde_hw_uidle *uidle,
FAL10_EXIT_CNT_MSK); FAL10_EXIT_CNT_MSK);
SDE_REG_WRITE(c, UIDLE_CTL, reg_val); SDE_REG_WRITE(c, UIDLE_CTL, reg_val);
if (!enable)
fal10_veto_regval |= (BIT(31) | BIT(0));
SDE_REG_WRITE(c, UIDLE_FAL10_VETO_OVERRIDE, fal10_veto_regval);
} }
static void sde_hw_uilde_active_override(struct sde_hw_uidle *uidle, static void sde_hw_uilde_active_override(struct sde_hw_uidle *uidle,