qcacmn: add reo bit to enable reo qref in fw

set register WCSS_UMAC_REO_R0_MISC_CTL 6th bit to 1
to enable reo wref from fw side.

Change-Id: Ib8d4a2f6e7f598d45ba2b2c628ed6f3929fc3337
CRs-Fixed: 3273558

hal/wifi3.0/hal_internal.h

@@ -768,6 +768,7 @@ struct hal_reo_params {
 	uint8_t alt_dst_ind_0;
 	/** padding */
 	uint8_t padding[2];
+	uint8_t reo_ref_peer_id_fix_enable;
 };
 
 /**

hal/wifi3.0/qcn9224/hal_9224.h

@@ -1677,6 +1677,11 @@ static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams,
 	reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
 		REO_REG_REG_BASE));
 
+	if (soc->version >= 2) {
+		struct hal_reo_params *reo_params = reoparams;
+
+		reo_params->reo_ref_peer_id_fix_enable = 1;
+	}
 	hal_reo_config_9224(soc, reg_val, reo_params);
 	/* Other ring enable bits and REO_ENABLE will be set by FW */
 

hal/wifi3.0/qcn9224/hal_9224_rx.h

@@ -84,6 +84,11 @@
 		reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL,		\
 				  FRAGMENT_DEST_RING,		\
 				  (reo_params)->frag_dst_ring); \
+		reg_val |= ((reo_params)->reo_ref_peer_id_fix_enable) << 6; \
+		HAL_REG_WRITE(soc,				\
+			      HWIO_REO_R0_MISC_CTL_ADDR(	\
+				REO_REG_REG_BASE),		\
+			      reg_val);				\
 	} while (0)
 
 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \