qcacmn: Add support for additional REO rings for Beryllium

Beryllium supports additional REO rings to cater increased bandwidth.
Enable additional REO rings.

Change-Id: I5124c92e30e4ac56a78b6f5f38d1c91a2933bba8
CRs-Fixed: 2930184
此提交包含在:
Manjunathappa Prakash
2021-04-13 02:54:29 -07:00
提交者 Madan Koyyalamudi
父節點 b845bfdce4
當前提交 cebffa806d
共有 11 個檔案被更改,包括 225 行新增51 行删除

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@@ -1055,7 +1055,16 @@ extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
#define REO_REMAP_SW4 4
#define REO_REMAP_RELEASE 5
#define REO_REMAP_FW 6
#define REO_REMAP_UNUSED 7
/*
* In Beryllium: 4 bits REO destination ring value is defined as: 0: TCL
* 1:SW1 2:SW2 3:SW3 4:SW4 5:Release 6:FW(WIFI) 7:SW5
* 8:SW6 9:SW7 10:SW8 11: NOT_USED.
*
*/
#define REO_REMAP_SW5 7
#define REO_REMAP_SW6 8
#define REO_REMAP_SW7 9
#define REO_REMAP_SW8 10
/*
* Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0

查看文件

@@ -1114,47 +1114,98 @@ hal_rx_flow_setup_fse_7850(uint8_t *rx_fst, uint32_t table_offset,
}
static
void hal_compute_reo_remap_ix2_ix3_7850(uint32_t *ring, uint32_t num_rings,
uint32_t *remap1, uint32_t *remap2)
void hal_compute_reo_remap_ix2_ix3_7850(uint32_t *ring_map,
uint32_t num_rings, uint32_t *remap1,
uint32_t *remap2)
{
switch (num_rings) {
case 3:
*remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
HAL_REO_REMAP_IX2(ring[1], 17) |
HAL_REO_REMAP_IX2(ring[2], 18) |
HAL_REO_REMAP_IX2(ring[0], 19) |
HAL_REO_REMAP_IX2(ring[1], 20) |
HAL_REO_REMAP_IX2(ring[2], 21) |
HAL_REO_REMAP_IX2(ring[0], 22) |
HAL_REO_REMAP_IX2(ring[1], 23);
/*
* The 4 bits REO destination ring value is defined as: 0: TCL
* 1:SW1 2:SW2 3:SW3 4:SW4 5:Release 6:FW(WIFI) 7:SW5
* 8:SW6 9:SW7 10:SW8 11: NOT_USED.
*
*/
uint32_t reo_dest_ring_map[] = {REO_REMAP_SW1, REO_REMAP_SW2,
REO_REMAP_SW3, REO_REMAP_SW4,
REO_REMAP_SW5, REO_REMAP_SW6,
REO_REMAP_SW7, REO_REMAP_SW8};
*remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
HAL_REO_REMAP_IX3(ring[0], 25) |
HAL_REO_REMAP_IX3(ring[1], 26) |
HAL_REO_REMAP_IX3(ring[2], 27) |
HAL_REO_REMAP_IX3(ring[0], 28) |
HAL_REO_REMAP_IX3(ring[1], 29) |
HAL_REO_REMAP_IX3(ring[2], 30) |
HAL_REO_REMAP_IX3(ring[0], 31);
switch (num_rings) {
default:
case 3:
*remap1 = HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 16) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 17) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[2], 18) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 19) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 20) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[2], 21) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 22) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 23);
*remap2 = HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 24) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 25) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[1], 26) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 27) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 28) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[1], 29) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 30) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 31);
break;
case 4:
*remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
HAL_REO_REMAP_IX2(ring[1], 17) |
HAL_REO_REMAP_IX2(ring[2], 18) |
HAL_REO_REMAP_IX2(ring[3], 19) |
HAL_REO_REMAP_IX2(ring[0], 20) |
HAL_REO_REMAP_IX2(ring[1], 21) |
HAL_REO_REMAP_IX2(ring[2], 22) |
HAL_REO_REMAP_IX2(ring[3], 23);
*remap1 = HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 16) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 17) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[2], 18) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[3], 19) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 20) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 21) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[2], 22) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[3], 23);
*remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
HAL_REO_REMAP_IX3(ring[1], 25) |
HAL_REO_REMAP_IX3(ring[2], 26) |
HAL_REO_REMAP_IX3(ring[3], 27) |
HAL_REO_REMAP_IX3(ring[0], 28) |
HAL_REO_REMAP_IX3(ring[1], 29) |
HAL_REO_REMAP_IX3(ring[2], 30) |
HAL_REO_REMAP_IX3(ring[3], 31);
*remap2 = HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 24) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[1], 25) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 26) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[3], 27) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 28) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[1], 29) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 30) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[3], 31);
break;
case 6:
*remap1 = HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 16) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 17) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[2], 18) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[4], 19) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[5], 20) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[6], 21) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 22) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 23);
*remap2 = HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 24) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[4], 25) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[5], 26) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[6], 27) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 28) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[1], 29) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 30) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[4], 31);
break;
case 8:
*remap1 = HAL_REO_REMAP_IX2(reo_dest_ring_map[0], 16) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[1], 17) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[2], 18) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[3], 19) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[4], 20) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[5], 21) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[6], 22) |
HAL_REO_REMAP_IX2(reo_dest_ring_map[7], 23);
*remap2 = HAL_REO_REMAP_IX3(reo_dest_ring_map[0], 24) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[1], 25) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[2], 26) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[3], 27) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[4], 28) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[5], 29) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[6], 30) |
HAL_REO_REMAP_IX3(reo_dest_ring_map[7], 31);
break;
}
}
@@ -1394,7 +1445,7 @@ struct hal_hw_srng_config hw_srng_table_7850[] = {
/* TODO: max_rings can populated by querying HW capabilities */
{ /* REO_DST */
.start_ring_id = HAL_SRNG_REO2SW1,
.max_rings = 4,
.max_rings = 8,
.entry_size = sizeof(struct reo_destination_ring) >> 2,
.lmac_ring = FALSE,
.ring_dir = HAL_SRNG_DST_RING,