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@@ -0,0 +1,365 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#include <linux/bits.h>
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+#include "ipa_i.h"
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+#include "ipahal.h"
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+#include "ipahal_reg.h"
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+#include "ipahal_tsp.h"
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+
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+/*
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+ * Every Producer can hold up to 16 K Queue elements and 8 Queues.
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+ * Thus, software allocates up to 512 Kbytes (32 bytes *16 K QEs) contiguously in memory.
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+ */
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+#define IPA_TSP_QM_DRAM_BYTESIZE (16384 * 32)
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+
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+static void __ipa_tsp_get_supported_constrains(void)
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+{
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+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_5) {
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+ struct ipahal_ipa_flavor_9 ipa_flavor_9;
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+
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+ ipahal_read_reg_fields(IPA_FLAVOR_9, &ipa_flavor_9);
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+ ipa3_ctx->tsp.ingr_tc_max = ipa_flavor_9.ipa_tsp_max_ingr_tc;
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+ ipa3_ctx->tsp.egr_ep_max = ipa_flavor_9.ipa_tsp_max_prod;
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+ ipa3_ctx->tsp.egr_tc_max = ipa_flavor_9.ipa_tsp_max_egr_tc;
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+ } else {
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+ ipa3_ctx->tsp.ingr_tc_max = 0;
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+ ipa3_ctx->tsp.egr_ep_max = 0;
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+ ipa3_ctx->tsp.egr_tc_max = 0;
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+
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+ IPAERR("TSP not supported. ingr_tc_max=%d egr_ep_max=%d egr_tc_max=%d\n",
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+ ipa3_ctx->tsp.ingr_tc_max, ipa3_ctx->tsp.egr_ep_max, ipa3_ctx->tsp.egr_tc_max);
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+ }
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+}
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+
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+int ipa_tsp_init(void)
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+{
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+ int i, ret = 0;
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+ gfp_t flag = GFP_KERNEL;
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+ dma_addr_t qm_tlv_base;
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+ u32 qm_tlv_size;
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+
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+ /*
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+ * Cache the TSP table size constrains
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+ */
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+ __ipa_tsp_get_supported_constrains();
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+ if (!ipa3_ctx->tsp.ingr_tc_max || !ipa3_ctx->tsp.egr_ep_max || !ipa3_ctx->tsp.egr_tc_max) {
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+ IPAERR("TSP not supported. ingr_tc_max=%d egr_ep_max=%d egr_tc_max=%d\n",
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+ ipa3_ctx->tsp.ingr_tc_max, ipa3_ctx->tsp.egr_ep_max, ipa3_ctx->tsp.egr_tc_max);
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+ return -EFAULT;
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+ }
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+
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+ /*
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+ * Allocate DMA accessible memory for HW commitable ipa3_ctx->tsp.ingr_tc_tbl,
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+ * ipa3_ctx->tsp.egr_ep_tbl and ipa3_ctx->tsp.egr_tc_tbl
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+ */
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+ ipa3_ctx->tsp.ingr_tc_tbl.size = ipa3_ctx->tsp.ingr_tc_max * IPA_TSP_INGR_TC_SIZE;
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+ ipa3_ctx->tsp.egr_ep_tbl.size = ipa3_ctx->tsp.egr_ep_max * IPA_TSP_EGR_EP_SIZE;
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+ ipa3_ctx->tsp.egr_tc_tbl.size = ipa3_ctx->tsp.egr_tc_max * IPA_TSP_EGR_TC_SIZE;
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+
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+ if (!ipa3_ctx->tsp.ingr_tc_tbl.size || !ipa3_ctx->tsp.egr_ep_tbl.size || !ipa3_ctx->tsp.egr_tc_tbl.size) {
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+ IPAERR("ingr_tc_tbl.size=%d egr_ep_tbl.size=%d egr_tc_tbl.size=%d\n",
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+ ipa3_ctx->tsp.ingr_tc_tbl.size, ipa3_ctx->tsp.egr_ep_tbl.size, ipa3_ctx->tsp.egr_tc_tbl.size);
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+ return -EFAULT;
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+ }
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+
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+ if (!ipa3_ctx->pdev || !&(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)) {
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+ IPAERR("ipa3_ctx->pdev=%16X &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)=%16X\n",
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+ ipa3_ctx->pdev, &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base));
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+ return -EFAULT;
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+ }
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+ IPAERR("ipa3_ctx->pdev=%16X &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base)=%16X\n",
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+ ipa3_ctx->pdev, &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base));
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+
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+ ipa3_ctx->tsp.ingr_tc_tbl.base = dma_alloc_coherent(ipa3_ctx->pdev,
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+ ipa3_ctx->tsp.ingr_tc_tbl.size, &(ipa3_ctx->tsp.ingr_tc_tbl.phys_base), GFP_KERNEL);
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+ if (!ipa3_ctx->tsp.ingr_tc_tbl.base) {
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+ IPAERR("Failed to allocate cache memory for ingress TC TSP table.\n");
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+ return -ENOMEM;
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+ }
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+
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+ ipa3_ctx->tsp.egr_ep_tbl.base = dma_alloc_coherent(ipa3_ctx->pdev,
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+ ipa3_ctx->tsp.egr_ep_tbl.size, &(ipa3_ctx->tsp.egr_ep_tbl.phys_base), GFP_KERNEL);
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+ if (!ipa3_ctx->tsp.egr_ep_tbl.base) {
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+ IPAERR("Failed to allocate cache memory for egress producer TSP table.\n");
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+ ret = -ENOMEM;
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+ goto free_ingr;
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+ }
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+
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+ ipa3_ctx->tsp.egr_tc_tbl.base = dma_alloc_coherent(ipa3_ctx->pdev,
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+ ipa3_ctx->tsp.egr_tc_tbl.size, &(ipa3_ctx->tsp.egr_tc_tbl.phys_base), GFP_KERNEL);
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+ if (!ipa3_ctx->tsp.egr_tc_tbl.base) {
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+ IPAERR("Failed to allocate cache memory for egress TC TSP table.\n");
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+ ret = -ENOMEM;
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+ goto free_ep;
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+ }
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+
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+ /*
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+ * Allocate configured producer array
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+ */
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+ ipa3_ctx->tsp.egr_ep_config =
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+ (enum ipa_client_type *)
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+ kzalloc(ipa3_ctx->tsp.egr_ep_max * sizeof(enum ipa_client_type), GFP_KERNEL);
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+
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+ if (ipa3_ctx->tsp.egr_ep_config == NULL) {
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+ IPAERR("Failed to allocate cache memory for egress producer config.\n");
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+ ret = -ENOMEM;
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+ goto free_egr;
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+ }
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+
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+ /*
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+ * Init configured producer array
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+ */
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+ for (i = 0; i < ipa3_ctx->tsp.egr_ep_max; i++)
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+ ipa3_ctx->tsp.egr_ep_config[i] = IPA_CLIENT_MAX;
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+ ipa3_ctx->tsp.egr_tc_range_mask = 0;
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+
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+ /*
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+ * Allocate memory for TLV-IN queues:
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+ * Every Producer can hold up to 16 K Queue elements and 8 Queues.
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+ * Thus, software allocates up to 512 Kbytes (32 bytes *16 K QEs) contiguously in memory.
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+ * Note: All queues of all PRODs have to be together in contiguous memory!
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+ * Must be 128B aligned.
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+ */
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+ qm_tlv_size = IPA_TSP_QM_DRAM_BYTESIZE;
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+ ipa3_ctx->tsp.qm_tlv_mem.size = qm_tlv_size + 128; // + 128 bytes to fit alignment
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+alloc:
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+ ipa3_ctx->tsp.qm_tlv_mem.base = dma_alloc_coherent(ipa3_ctx->pdev,
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+ ipa3_ctx->tsp.qm_tlv_mem.size, &(ipa3_ctx->tsp.qm_tlv_mem.phys_base), flag);
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+ if (!ipa3_ctx->tsp.qm_tlv_mem.base) {
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+ if (flag == GFP_KERNEL) {
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+ flag = GFP_ATOMIC;
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+ goto alloc;
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+ }
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+ IPAERR("fail to alloc DMA buff of size %d\n", ipa3_ctx->tsp.qm_tlv_mem.size);
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+ ret = -ENOMEM;
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+ goto free_ep_conf;
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+ }
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+
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+ /* Get 128B aligned address inside the buffer */
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+ qm_tlv_base = ipa3_ctx->tsp.qm_tlv_mem.phys_base;
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+ if (qm_tlv_base & 0x7F) {
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+ qm_tlv_base += 0x80;
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+ qm_tlv_base &= !0x7F;
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+ }
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+
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+ ipahal_write_reg(IPA_TSP_QM_EXTERNAL_BADDR_LSB, qm_tlv_base & 0xFFFFFFFF);
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+ ipahal_write_reg(IPA_TSP_QM_EXTERNAL_BADDR_MSB, qm_tlv_base >> 32);
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+ ipahal_write_reg(IPA_TSP_QM_EXTERNAL_SIZE, qm_tlv_size >> 12); //Size in 4kB resolution
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+
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+ goto done;
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+
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+free_ep_conf:
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+ kfree(ipa3_ctx->tsp.egr_ep_config);
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+ ipa3_ctx->tsp.egr_ep_config = NULL;
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+free_egr:
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+ dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->tsp.egr_tc_tbl.size,
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+ ipa3_ctx->tsp.egr_tc_tbl.base, ipa3_ctx->tsp.egr_tc_tbl.phys_base);
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+ ipa3_ctx->tsp.egr_tc_tbl.base = NULL;
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+free_ep:
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+ dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->tsp.egr_ep_tbl.size,
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+ ipa3_ctx->tsp.egr_ep_tbl.base, ipa3_ctx->tsp.egr_ep_tbl.phys_base);
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+ ipa3_ctx->tsp.egr_ep_tbl.base = NULL;
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+free_ingr:
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+ dma_free_coherent(ipa3_ctx->pdev, ipa3_ctx->tsp.ingr_tc_tbl.size,
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+ ipa3_ctx->tsp.ingr_tc_tbl.base, ipa3_ctx->tsp.ingr_tc_tbl.phys_base);
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+ ipa3_ctx->tsp.ingr_tc_tbl.base = NULL;
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+done:
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+ return ret;
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+}
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+
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+int ipa_tsp_get_ingr_tc(u8 index, struct ipa_ioc_tsp_ingress_class_params *output)
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+{
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+ /* The function is internal only, assuming valid params */
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+
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+ ipahal_tsp_parse_hw_ingr_tc(ipa3_ctx->tsp.ingr_tc_tbl.base, index, output);
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+ output->include_l2_len = !!(ipahal_read_reg(IPA_TSP_INGRESS_POLICING_CFG) & (0x1 << index));
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+
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+ return 0;
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+}
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+
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+int ipa_tsp_get_egr_ep(u8 index, struct ipa_ioc_tsp_egress_prod_params *output)
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+{
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+ u32 regval;
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+ struct ipa_ep_cfg_prod_cfg prod_cfg;
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+
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+ /* The function is internal only, assuming valid params */
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+
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+ ipahal_tsp_parse_hw_egr_ep(ipa3_ctx->tsp.egr_ep_tbl.base, index, output);
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+
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+ output->client = ipa3_ctx->tsp.egr_ep_config[index];
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+
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+ regval = ipahal_read_reg_n_fields(IPA_ENDP_INIT_PROD_CFG_n,
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+ ipa3_get_ep_mapping(output->client), (void *)&prod_cfg);
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+
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+ output->max_out_bytes = prod_cfg.max_output_size << 6; // max_output_size*64
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+ output->policing_by_max_out = prod_cfg.max_output_size_drop_enable;
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+ output->tc_lo = prod_cfg.egress_tc_lowest;
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+ output->tc_hi = prod_cfg.egress_tc_highest;
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+
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+ return 0;
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+}
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+
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+int ipa_tsp_get_egr_tc(u8 index, struct ipa_ioc_tsp_egress_class_params *output)
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+{
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+ /* The function is internal only, assuming valid params */
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+
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+ ipahal_tsp_parse_hw_egr_tc(ipa3_ctx->tsp.egr_tc_tbl.base, index, output);
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+
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+ return 0;
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+}
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+
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+int ipa_tsp_set_ingr_tc(u8 index, const struct ipa_ioc_tsp_ingress_class_params *input)
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+{
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+ /* The function is internal only, assuming valid params */
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+
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+ ipahal_tsp_fill_hw_ingr_tc(input, ipa3_ctx->tsp.ingr_tc_tbl.base, index);
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+ ipahal_write_reg_mask(IPA_TSP_INGRESS_POLICING_CFG,
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+ 0x1 << input->include_l2_len, 0x1 << index);
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+
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+ return 0;
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+}
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+
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+int ipa_tsp_set_egr_ep(u8 index, const struct ipa_ioc_tsp_egress_prod_params *input)
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+{
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+ u32 regval, ep_index, ep_tc_mask, new_tc_range_mask;
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+ struct ipa_ep_cfg_prod_cfg prod_cfg;
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+ bool cleanup = false;
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+
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+ ep_tc_mask = GENMASK(input->tc_hi, input->tc_lo);
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+ new_tc_range_mask = ipa3_ctx->tsp.egr_tc_range_mask;
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+
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+ ep_index = ipa3_get_ep_mapping(ipa3_ctx->tsp.egr_ep_config[index]);
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+ regval = ipahal_read_reg_n_fields(
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+ IPA_ENDP_INIT_PROD_CFG_n, ep_index, (void *)&prod_cfg);
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+
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+ if (ipa3_ctx->tsp.egr_ep_config[index] != IPA_CLIENT_MAX &&
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+ ipa3_ctx->tsp.egr_ep_config[index] != input->client) {
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+ cleanup = true;
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+ new_tc_range_mask &= !GENMASK(prod_cfg.egress_tc_highest,prod_cfg.egress_tc_lowest);
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+ }
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+
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+ if (ep_tc_mask & new_tc_range_mask) {
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+ IPAERR("New egress TC range overlaps existing.\n");
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+ return -EINVAL;
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+ }
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+
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+ if (cleanup) {
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+ /* Cleanup old producer config */
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+ prod_cfg.tsp_enable = false;
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+ prod_cfg.egress_tc_lowest = 0;
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+ prod_cfg.egress_tc_highest = 0;
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+ if (ipa3_cfg_ep_prod_cfg(ep_index, &prod_cfg) != 0) {
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+ IPAERR("Failed configuring the producer EP.\n");
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+ return -EFAULT;
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+ }
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+ }
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+
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+ prod_cfg.tsp_enable = true;
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+ prod_cfg.tsp_idx = index;
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+ prod_cfg.max_output_size = input->max_out_bytes >> 6; // max_out_bytes/64
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+ prod_cfg.max_output_size_drop_enable = input->policing_by_max_out;
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+ prod_cfg.egress_tc_lowest = input->tc_lo;
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+ prod_cfg.egress_tc_highest = input->tc_hi;
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+ if (ipa3_cfg_ep_prod_cfg(ipa3_get_ep_mapping(input->client), &prod_cfg) != 0) {
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+ IPAERR("Failed configuring the producer EP.\n");
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+ return -EFAULT;
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+ }
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+
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+ ipa3_ctx->tsp.egr_ep_config[index] = input->client;
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+ ipa3_ctx->tsp.egr_tc_range_mask = new_tc_range_mask | ep_tc_mask;
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+ ipahal_tsp_fill_hw_egr_ep(input, ipa3_ctx->tsp.egr_ep_tbl.base, index);
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+
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+ return 0;
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+}
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+
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+int ipa_tsp_set_egr_tc(u8 index, const struct ipa_ioc_tsp_egress_class_params *input)
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+{
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+ /* The function is internal only, assuming valid params */
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+
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+ ipahal_tsp_fill_hw_egr_tc(input, ipa3_ctx->tsp.egr_tc_tbl.base, index);
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+
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+ /*
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+ * If guaranteed_rate and guaranteed_burst are set to 0,
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+ * the guaranteed bandwidth rate will be disabled,
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+ * and only maximal bandwidth rate will be considered.
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+ */
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+ if (input->guaranteed_rate || input->guaranteed_burst)
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+ ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x1 << index, 0x1 << index);
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+ else
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+ ipahal_write_reg_mask(IPA_TSP_EGRESS_POLICING_CFG, 0x0, 0x1 << index);
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+
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+ return 0;
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+}
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+
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+int ipa_tsp_commit(void)
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+{
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+ int ret = 0;
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+ u32 ingr_tc_base, egr_tc_base, prod_base;
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+ void *ingr_tc_mmio, *egr_tc_mmio, *prod_mmio;
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+
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+ ingr_tc_base = ipahal_read_reg(IPA_RAM_INGRESS_POLICER_DB_BASE_ADDR);
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+ egr_tc_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_TC_DB_BASE_ADDR);
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+ prod_base = ipahal_read_reg(IPA_RAM_EGRESS_SHAPING_PROD_DB_BASE_ADDR);
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+
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+ /* map IPA SRAM */
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+ ingr_tc_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + ingr_tc_base,
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+ ipa3_ctx->tsp.ingr_tc_tbl.size);
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+ egr_tc_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + egr_tc_base,
|
|
|
+ ipa3_ctx->tsp.egr_tc_tbl.size);
|
|
|
+ prod_mmio = ioremap(ipa3_ctx->ipa_wrapper_base + prod_base,
|
|
|
+ ipa3_ctx->tsp.egr_ep_tbl.size);
|
|
|
+ if (!ingr_tc_mmio || !egr_tc_mmio || !prod_mmio) {
|
|
|
+ IPAERR("Failed to ioremap TSP SRAM\n");
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto end;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The tables are located in the HW SRAM area, and we can't issue the DMA IMM, because
|
|
|
+ * the offset field is restricted to 16 addresses in it.
|
|
|
+ * Therefore, we do memcopy instead, but the infrastructure will be ready for DMA
|
|
|
+ * in future IPA versions.
|
|
|
+ */
|
|
|
+ memcpy_toio(ingr_tc_mmio, ipa3_ctx->tsp.ingr_tc_tbl.base, ipa3_ctx->tsp.ingr_tc_tbl.size);
|
|
|
+ memcpy_toio(egr_tc_mmio, ipa3_ctx->tsp.egr_tc_tbl.base, ipa3_ctx->tsp.egr_tc_tbl.size);
|
|
|
+ memcpy_toio(prod_mmio, ipa3_ctx->tsp.egr_ep_tbl.base, ipa3_ctx->tsp.egr_ep_tbl.size);
|
|
|
+
|
|
|
+end:
|
|
|
+ if (ingr_tc_mmio)
|
|
|
+ iounmap(ingr_tc_mmio);
|
|
|
+ if (egr_tc_mmio)
|
|
|
+ iounmap(egr_tc_mmio);
|
|
|
+ if (prod_mmio)
|
|
|
+ iounmap(prod_mmio);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+int ipa_tsp_reset(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ struct ipa_ep_cfg_prod_cfg prod_cfg = {0};
|
|
|
+
|
|
|
+ for (i = 0;
|
|
|
+ i < ipa3_ctx->tsp.egr_ep_max && ipa3_ctx->tsp.egr_ep_config[i] < IPA_CLIENT_MAX; i++)
|
|
|
+ ipa3_cfg_ep_prod_cfg(ipa3_get_ep_mapping(ipa3_ctx->tsp.egr_ep_config[i]),
|
|
|
+ &prod_cfg);
|
|
|
+
|
|
|
+ if (ipa3_ctx->tsp.ingr_tc_tbl.base)
|
|
|
+ memset(ipa3_ctx->tsp.ingr_tc_tbl.base, 0, ipa3_ctx->tsp.ingr_tc_tbl.size);
|
|
|
+ if (ipa3_ctx->tsp.egr_tc_tbl.base)
|
|
|
+ memset(ipa3_ctx->tsp.egr_tc_tbl.base, 0, ipa3_ctx->tsp.egr_tc_tbl.size);
|
|
|
+ if (ipa3_ctx->tsp.egr_ep_tbl.base)
|
|
|
+ memset(ipa3_ctx->tsp.egr_ep_tbl.base, 0, ipa3_ctx->tsp.egr_ep_tbl.size);
|
|
|
+
|
|
|
+ /* Reinit configured producer array */
|
|
|
+ for (i = 0; i < ipa3_ctx->tsp.egr_ep_max; i++)
|
|
|
+ ipa3_ctx->tsp.egr_ep_config[i] = IPA_CLIENT_MAX;
|
|
|
+
|
|
|
+ ipa3_ctx->tsp.egr_tc_range_mask = 0;
|
|
|
+
|
|
|
+ return ipa_tsp_commit();
|
|
|
+}
|
|
|
+
|
Ilia Lin