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asoc: codecs: Update register initialization sequence

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Add latest register sequence.
Remove version 1_2.
Update header files with latest registers.

Change-Id: I92f56e5ec2be4e695d42cec8610b9b9300410b02
Signed-off-by: Matthew Rice <mrice@codeaurora.org>
This commit is contained in:
Matthew Rice
2021-09-22 14:27:51 -07:00
committed by Gerrit - the friendly Code Review server
parent 179ce4f13f
commit cdcdcac0df
7 changed files with 289 additions and 201 deletions
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1
asoc/codecs/wsa884x/internal.h
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@@ -30,7 +30,6 @@
#define WSA884X_VARIANT_ENTRY_SIZE 32 #define WSA884X_VARIANT_ENTRY_SIZE 32
#define WSA884X_VERSION_1_0 0 #define WSA884X_VERSION_1_0 0
#define WSA884X_VERSION_1_1 1
enum { enum {
G_21DB = 0, G_21DB = 0,

189
asoc/codecs/wsa884x/wsa884x-reg-masks.h
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@@ -9,79 +9,148 @@
#include <linux/device.h> #include <linux/device.h>
#include "wsa884x-registers.h" #include "wsa884x-registers.h"
/*
* Use in conjunction with wsa884x-reg-shifts.c for field values.
* field_value = (register_value & field_mask) >> field_shift
*/
#define FIELD_MASK(register_name, field_name) \ #define FIELD_MASK(register_name, field_name) \
WSA884X_##register_name##_##field_name##_MASK WSA884X_##register_name##_##field_name##_MASK
#define WSA884X_VBAT_SNS_BOP_FREQ_MASK 0x60 /* WSA884X_VSENSE1 Fields: */
#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0 #define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0
#define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_MASK 0x10
#define WSA884X_VSENSE1_IDLE_MODE_CTL_MASK 0x0c
#define WSA884X_VSENSE1_VOCM_AMP_CTL_MASK 0x03
/* WSA884X_ADC_2 Fields: */
#define WSA884X_ADC_2_ATEST_SEL_CAL_REF_MASK 0x80
#define WSA884X_ADC_2_ISNS_LOAD_STORED_MASK 0x40 #define WSA884X_ADC_2_ISNS_LOAD_STORED_MASK 0x40
#define WSA884X_ADC_6_INTRLV_RST_OVRD_MASK 0x02 #define WSA884X_ADC_2_EN_DET_MASK 0x20
#define WSA884X_ADC_2_EN_ATEST_REF_MASK 0x10
#define WSA884X_ADC_2_EN_ATEST_INT_MASK 0x0e
#define WSA884X_ADC_2_D_ADC_REG_EN_MASK 0x01
/* WSA884X_ADC_7 Fields: */
#define WSA884X_ADC_7_CLAMPON_MASK 0x80
#define WSA884X_ADC_7_CAL_LOOP_TRIM_MASK 0x70
#define WSA884X_ADC_7_REG_TRIM_EN_MASK 0x08
#define WSA884X_ADC_7_EN_AZ_REG_MASK 0x04 #define WSA884X_ADC_7_EN_AZ_REG_MASK 0x04
#define WSA884X_ADC_7_EN_SAR_REG_MASK 0x02 #define WSA884X_ADC_7_EN_SAR_REG_MASK 0x02
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80 #define WSA884X_ADC_7_EN_SW_CURRENT_REG_MASK 0x01
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c /* WSA884X_BOP_DEGLITCH_CTL Fields: */
#define WSA884X_BOOST_MISC_SPKR_RDY_CTL_MASK 0x60 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e
#define WSA884X_CKWD_CTL_0_CKWD_FDIV_SEL_MASK 0x60 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x01
#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f /* WSA884X_CDC_SPK_DSM_A2_0 Fields: */
#define WSA884X_CHIP_ID0_BYTE_0_MASK 0xff #define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_MASK 0xff
#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01 /* WSA884X_CDC_SPK_DSM_A2_1 Fields: */
#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_MASK 0x0f
/* WSA884X_CDC_SPK_DSM_A3_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_MASK 0xff
/* WSA884X_CDC_SPK_DSM_A3_1 Fields: */
#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_MASK 0x07
/* WSA884X_CDC_SPK_DSM_A4_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_MASK 0xff
/* WSA884X_CDC_SPK_DSM_A5_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_MASK 0xff
/* WSA884X_CDC_SPK_DSM_A6_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_MASK 0xff
/* WSA884X_CDC_SPK_DSM_A7_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_MASK 0xff
/* WSA884X_CDC_SPK_DSM_C_0 Fields: */
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
/* WSA884X_CDC_SPK_DSM_C_2 Fields: */
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
/* WSA884X_CDC_SPK_DSM_C_3 Fields: */
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
/* WSA884X_CDC_SPK_DSM_R1 Fields: */
#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_MASK 0xff
/* WSA884X_CDC_SPK_DSM_R2 Fields: */
#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_MASK 0xff
/* WSA884X_CDC_SPK_DSM_R3 Fields: */
#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_MASK 0xff
/* WSA884X_CDC_SPK_DSM_R4 Fields: */
#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_MASK 0xff
/* WSA884X_CDC_SPK_DSM_R5 Fields: */
#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_MASK 0xff
/* WSA884X_CDC_SPK_DSM_R6 Fields: */
#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_MASK 0xff
/* WSA884X_CDC_SPK_DSM_R7 Fields: */
#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_MASK 0xff
/* WSA884X_DRE_CTL_0 Fields: */
#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
/* WSA884X_GAIN_RAMPING_MIN Fields: */
#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK 0x1f
/* WSA884X_CLSH_SOFT_MAX Fields: */
#define WSA884X_CLSH_SOFT_MAX_SOFT_MAX_MASK 0xff
/* WSA884X_CLSH_VTH1 Fields: */
#define WSA884X_CLSH_VTH1_CLSH_VTH1_MASK 0xff
/* WSA884X_CLSH_VTH10 Fields: */
#define WSA884X_CLSH_VTH10_CLSH_VTH10_MASK 0xff
/* WSA884X_CLSH_VTH11 Fields: */
#define WSA884X_CLSH_VTH11_CLSH_VTH11_MASK 0xff
/* WSA884X_CLSH_VTH12 Fields: */
#define WSA884X_CLSH_VTH12_CLSH_VTH12_MASK 0xff
/* WSA884X_CLSH_VTH13 Fields: */
#define WSA884X_CLSH_VTH13_CLSH_VTH13_MASK 0xff
/* WSA884X_CLSH_VTH14 Fields: */
#define WSA884X_CLSH_VTH14_CLSH_VTH14_MASK 0xff
/* WSA884X_CLSH_VTH15 Fields: */
#define WSA884X_CLSH_VTH15_CLSH_VTH15_MASK 0xff
/* WSA884X_ANA_WO_CTL_0 Fields: */
#define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK 0xc0
#define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK 0x3c
#define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK 0x02
#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK 0x01
/* WSA884X_ANA_WO_CTL_1 Fields: */
#define WSA884X_ANA_WO_CTL_1_BOOST_SHARE_EN_MASK 0x08
#define WSA884X_ANA_WO_CTL_1_EXT_VDDSPK_EN_MASK 0x07
/* WSA884X_DRE_CTL_1 Fields: */
#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
/* WSA884X_VBAT_THRM_FLT_CTL Fields: */
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK 0xe0
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_MASK 0x10
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_MASK 0x01
/* WSA884X_PDM_WD_CTL Fields: */
#define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK 0x04
#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK 0x02
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
/* WSA884X_PA_FSM_BYP_CTL Fields: */
#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_MASK 0x01 #define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_MASK 0x01
/* WSA884X_TADC_VALUE_CTL Fields: */
#define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_MASK 0x02
#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01
/* WSA884X_PA_FSM_BYP0 Fields: */
#define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK 0x80 #define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK 0x80
#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK 0x40 #define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK 0x40
#define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK 0x20 #define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK 0x20
#define WSA884X_PA_FSM_BYP0_PA_EN_MASK 0x10
#define WSA884X_PA_FSM_BYP0_BOOST_EN_MASK 0x08
#define WSA884X_PA_FSM_BYP0_BG_EN_MASK 0x04 #define WSA884X_PA_FSM_BYP0_BG_EN_MASK 0x04
#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK 0x02 #define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK 0x02
#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK 0x01 #define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK 0x01
#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01 /* WSA884X_PA_FSM_BYP1 Fields: */
#define WSA884X_TEMP_CONFIG0_CTL_THRD_SAF2WAR_MASK 0x07 #define WSA884X_PA_FSM_BYP1_NG_MODE_MASK 0xc0
#define WSA884X_TEMP_CONFIG1_CTL_THRD_WAR2SAF_MASK 0x07 #define WSA884X_PA_FSM_BYP1_PWRSAV_CTL_MASK 0x20
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e #define WSA884X_PA_FSM_BYP1_RAMP_DOWN_MASK 0x10
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_MASK 0x01 #define WSA884X_PA_FSM_BYP1_RAMP_UP_MASK 0x08
#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_MASK 0xff #define WSA884X_PA_FSM_BYP1_BLEEDER_EN_MASK 0x04
#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_MASK 0x0f #define WSA884X_PA_FSM_BYP1_PA_MAIN_EN_MASK 0x02
#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_MASK 0xff #define WSA884X_PA_FSM_BYP1_PA_AUX_EN_MASK 0x01
#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_MASK 0x07 /* WSA884X_PA_FSM_EN Fields: */
#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_MASK 0xff #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01
#define WSA884X_CDC_SPK_DSM_A4_1_COEF_A4_MASK 0x03 /* WSA884X_OTP_REG_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_MASK 0xff
#define WSA884X_CDC_SPK_DSM_A5_1_COEF_A5_MASK 0x03
#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_MASK 0xff
#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_MASK 0xff
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
#define WSA884X_CDC_SPK_DSM_C_1_COEF_C5_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_1_COEF_C4_MASK 0x0f
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_MASK 0xff
#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_MASK 0xff
#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_MASK 0xff
#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_MASK 0xff
#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_MASK 0xff
#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_MASK 0xff
#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_MASK 0xff
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
#define WSA884X_TAGC_CTL_THERMAL_THRESH_MASK 0x0e
#define WSA884X_TAGC_CTL_THERMAL_AGC_EN_MASK 0x01
#define WSA884X_TAGC_TIME_REL_TIME_MASK 0x30
#define WSA884X_VAGC_CTL_VBAT_AGC_EN_MASK 0x01
#define WSA884X_VAGC_TIME_REL_TIME_MASK 0x0c
#define WSA884X_VAGC_TIME_HLD_TIME_MASK 0x03
#define WSA884X_VAGC_ATTN_LVL_2_VBAT_ATTN_LVL_MASK 0x1f
#define WSA884X_VAGC_ATTN_LVL_3_VBAT_ATTN_LVL_MASK 0x1f
#define WSA884X_OTP_REG_0_WSA884X_ID_MASK 0x0f #define WSA884X_OTP_REG_0_WSA884X_ID_MASK 0x0f
#define WSA884X_OTP_REG_1_LOW_TEMP_MSB_MASK 0xff /* WSA884X_CHIP_ID0 Fields: */
#define WSA884X_OTP_REG_2_LOW_TEMP_LSB_MASK 0xc0 #define WSA884X_CHIP_ID0_BYTE_0_MASK 0xff
#define WSA884X_OTP_REG_3_HIGH_TEMP_MSB_MASK 0xff /* WSA884X_CHIP_ID1 Fields: */
#define WSA884X_OTP_REG_4_HIGH_TEMP_LSB_MASK 0xc0 #define WSA884X_CHIP_ID1_BYTE_1_MASK 0xff
#define WSA884X_DRE_IDLE_DET_CTL_PA_OFF_FORCE_EN_MASK 0x40 /* WSA884X_CHIP_ID2 Fields: */
#define WSA884X_DRE_IDLE_DET_CTL_PDM_WD_FORCE_EN_MASK 0x20 #define WSA884X_CHIP_ID2_BYTE_2_MASK 0xff
#define WSA884X_DRE_IDLE_DET_CTL_DRE_IDLE_FORCE_EN_MASK 0x10 /* WSA884X_CHIP_ID3 Fields: */
#define WSA884X_DRE_IDLE_DET_CTL_DRE_FORCE_VALUE_MASK 0x0f #define WSA884X_CHIP_ID3_BYTE_3_MASK 0xff
#endif /* WSA884X_REG_MASKS_H */ #endif /* WSA884X_REG_MASKS_H */

182
asoc/codecs/wsa884x/wsa884x-reg-shifts.h
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@@ -9,79 +9,137 @@
#include <linux/device.h> #include <linux/device.h>
#include "wsa884x-registers.h" #include "wsa884x-registers.h"
/*
* Use in conjunction with wsa884x-reg-masks.c for field values.
* field_value = (register_value & field_mask) >> field_shift
*/
#define FIELD_SHIFT(register_name, field_name) \ #define FIELD_SHIFT(register_name, field_name) \
WSA884X_##register_name##_##field_name##_SHIFT WSA884X_##register_name##_##field_name##_SHIFT
#define WSA884X_VBAT_SNS_BOP_FREQ_SHIFT 0x05 /* WSA884X_VSENSE1 Fields: */
#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 0x05 #define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 0x05
#define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_SHIFT 0x04
#define WSA884X_VSENSE1_IDLE_MODE_CTL_SHIFT 0x02
#define WSA884X_VSENSE1_VOCM_AMP_CTL_SHIFT 0x00
/* WSA884X_ADC_2 Fields: */
#define WSA884X_ADC_2_ATEST_SEL_CAL_REF_SHIFT 0x07
#define WSA884X_ADC_2_ISNS_LOAD_STORED_SHIFT 0x06 #define WSA884X_ADC_2_ISNS_LOAD_STORED_SHIFT 0x06
#define WSA884X_ADC_6_INTRLV_RST_OVRD_SHIFT 0x01 #define WSA884X_ADC_2_EN_DET_SHIFT 0x05
#define WSA884X_ADC_2_EN_ATEST_REF_SHIFT 0x04
#define WSA884X_ADC_2_EN_ATEST_INT_SHIFT 0x01
#define WSA884X_ADC_2_D_ADC_REG_EN_SHIFT 0x00
/* WSA884X_ADC_7 Fields: */
#define WSA884X_ADC_7_CLAMPON_SHIFT 0x07
#define WSA884X_ADC_7_CAL_LOOP_TRIM_SHIFT 0x04
#define WSA884X_ADC_7_REG_TRIM_EN_SHIFT 0x03
#define WSA884X_ADC_7_EN_AZ_REG_SHIFT 0x02 #define WSA884X_ADC_7_EN_AZ_REG_SHIFT 0x02
#define WSA884X_ADC_7_EN_SAR_REG_SHIFT 0x01 #define WSA884X_ADC_7_EN_SAR_REG_SHIFT 0x01
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 0x07 #define WSA884X_ADC_7_EN_SW_CURRENT_REG_SHIFT 0x00
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 0x02 /* WSA884X_BOP_DEGLITCH_CTL Fields: */
#define WSA884X_BOOST_MISC_SPKR_RDY_CTL_SHIFT 0x05 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 0x01
#define WSA884X_CKWD_CTL_0_CKWD_FDIV_SEL_SHIFT 0x05 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0x00
#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0x00 /* WSA884X_CDC_SPK_DSM_A2_0 Fields: */
#define WSA884X_CHIP_ID0_BYTE_0_SHIFT 0x00 #define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_SHIFT 0x00
#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0x00 /* WSA884X_CDC_SPK_DSM_A2_1 Fields: */
#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_A3_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_A3_1 Fields: */
#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_A4_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_A5_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_A6_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_A7_0 Fields: */
#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_C_0 Fields: */
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 0x04
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_C_2 Fields: */
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 0x04
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_C_3 Fields: */
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R1 Fields: */
#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R2 Fields: */
#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R3 Fields: */
#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R4 Fields: */
#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R5 Fields: */
#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R6 Fields: */
#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_SHIFT 0x00
/* WSA884X_CDC_SPK_DSM_R7 Fields: */
#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_SHIFT 0x00
/* WSA884X_DRE_CTL_0 Fields: */
#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 0x04
#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0x00
/* WSA884X_GAIN_RAMPING_MIN Fields: */
#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0x00
/* WSA884X_CLSH_SOFT_MAX Fields: */
#define WSA884X_CLSH_SOFT_MAX_SOFT_MAX_SHIFT 0x00
/* WSA884X_CLSH_VTH1 Fields: */
#define WSA884X_CLSH_VTH1_CLSH_VTH1_SHIFT 0x00
/* WSA884X_CLSH_VTH10 Fields: */
#define WSA884X_CLSH_VTH10_CLSH_VTH10_SHIFT 0x00
/* WSA884X_CLSH_VTH11 Fields: */
#define WSA884X_CLSH_VTH11_CLSH_VTH11_SHIFT 0x00
/* WSA884X_CLSH_VTH12 Fields: */
#define WSA884X_CLSH_VTH12_CLSH_VTH12_SHIFT 0x00
/* WSA884X_CLSH_VTH13 Fields: */
#define WSA884X_CLSH_VTH13_CLSH_VTH13_SHIFT 0x00
/* WSA884X_CLSH_VTH14 Fields: */
#define WSA884X_CLSH_VTH14_CLSH_VTH14_SHIFT 0x00
/* WSA884X_CLSH_VTH15 Fields: */
#define WSA884X_CLSH_VTH15_CLSH_VTH15_SHIFT 0x00
/* WSA884X_ANA_WO_CTL_0 Fields: */
#define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_SHIFT 0x06
#define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_SHIFT 0x02
#define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_SHIFT 0x01
#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_SHIFT 0x00
/* WSA884X_ANA_WO_CTL_1 Fields: */
#define WSA884X_ANA_WO_CTL_1_BOOST_SHARE_EN_SHIFT 0x03
#define WSA884X_ANA_WO_CTL_1_EXT_VDDSPK_EN_SHIFT 0x00
/* WSA884X_DRE_CTL_1 Fields: */
#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 0x01
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0x00
/* WSA884X_VBAT_THRM_FLT_CTL Fields: */
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 0x05
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 0x04
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 0x01
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0x00
/* WSA884X_PDM_WD_CTL Fields: */
#define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 0x02
#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 0x01
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0x00
/* WSA884X_PA_FSM_BYP_CTL Fields: */
#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_SHIFT 0x00 #define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_SHIFT 0x00
/* WSA884X_TADC_VALUE_CTL Fields: */
#define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_SHIFT 0x01
#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0x00
/* WSA884X_PA_FSM_BYP0 Fields: */
#define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 0x07 #define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 0x07
#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 0x06 #define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 0x06
#define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 0x05 #define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 0x05
#define WSA884X_PA_FSM_BYP0_PA_EN_SHIFT 0x04
#define WSA884X_PA_FSM_BYP0_BOOST_EN_SHIFT 0x03
#define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 0x02 #define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 0x02
#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 0x01 #define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 0x01
#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0x00 #define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0x00
#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0x00 /* WSA884X_PA_FSM_BYP1 Fields: */
#define WSA884X_TEMP_CONFIG0_CTL_THRD_SAF2WAR_SHIFT 0x00 #define WSA884X_PA_FSM_BYP1_NG_MODE_SHIFT 0x06
#define WSA884X_TEMP_CONFIG1_CTL_THRD_WAR2SAF_SHIFT 0x00 #define WSA884X_PA_FSM_BYP1_PWRSAV_CTL_SHIFT 0x05
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 0x01 #define WSA884X_PA_FSM_BYP1_RAMP_DOWN_SHIFT 0x04
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0x00 #define WSA884X_PA_FSM_BYP1_RAMP_UP_SHIFT 0x03
#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_SHIFT 0x00 #define WSA884X_PA_FSM_BYP1_BLEEDER_EN_SHIFT 0x02
#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_SHIFT 0x00 #define WSA884X_PA_FSM_BYP1_PA_MAIN_EN_SHIFT 0x01
#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_SHIFT 0x00 #define WSA884X_PA_FSM_BYP1_PA_AUX_EN_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_SHIFT 0x00 /* WSA884X_PA_FSM_EN Fields: */
#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_SHIFT 0x00 #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_A4_1_COEF_A4_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_A5_1_COEF_A5_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 0x04
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_C_1_COEF_C5_SHIFT 0x04
#define WSA884X_CDC_SPK_DSM_C_1_COEF_C4_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 0x04
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_SHIFT 0x00
#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_SHIFT 0x00
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0x00
#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 0x04
#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0x00
#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 0x01
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0x00
#define WSA884X_TAGC_CTL_THERMAL_THRESH_SHIFT 0x01
#define WSA884X_TAGC_CTL_THERMAL_AGC_EN_SHIFT 0x00
#define WSA884X_TAGC_TIME_REL_TIME_SHIFT 0x04
#define WSA884X_VAGC_CTL_VBAT_AGC_EN_SHIFT 0x00
#define WSA884X_VAGC_TIME_REL_TIME_SHIFT 0x02
#define WSA884X_VAGC_TIME_HLD_TIME_SHIFT 0x00
#define WSA884X_VAGC_ATTN_LVL_2_VBAT_ATTN_LVL_SHIFT 0x00
#define WSA884X_VAGC_ATTN_LVL_3_VBAT_ATTN_LVL_SHIFT 0x00
#define WSA884X_OTP_REG_0_WSA884X_ID_SHIFT 0x00
#define WSA884X_OTP_REG_1_LOW_TEMP_MSB_SHIFT 0x00
#define WSA884X_OTP_REG_2_LOW_TEMP_LSB_SHIFT 0x06
#define WSA884X_OTP_REG_3_HIGH_TEMP_MSB_SHIFT 0x00
#define WSA884X_OTP_REG_4_HIGH_TEMP_LSB_SHIFT 0x06
#define WSA884X_DRE_IDLE_DET_CTL_PA_OFF_FORCE_EN_SHIFT 0x06
#define WSA884X_DRE_IDLE_DET_CTL_PDM_WD_FORCE_EN_SHIFT 0x05
#define WSA884X_DRE_IDLE_DET_CTL_DRE_IDLE_FORCE_EN_SHIFT 0x04
#define WSA884X_DRE_IDLE_DET_CTL_DRE_FORCE_VALUE_SHIFT 0x00
#endif /* WSA884X_REG_SHIFTS_H */ #endif /* WSA884X_REG_SHIFTS_H */

2
asoc/codecs/wsa884x/wsa884x-registers.h
View File

@@ -320,7 +320,7 @@ enum {
#define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE+0x500) #define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE+0x500)
#define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE+0x00) #define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE+0x00)
#define WSA884X_BST_CFG (WSA884X_DIG_CTRL1_BASE+0x01) #define WSA884X_VPHX_SYS_EN_STATUS (WSA884X_DIG_CTRL1_BASE+0x01)
#define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE+0x04) #define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE+0x04)
#define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE+0x05) #define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE+0x05)
#define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE+0x10) #define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE+0x10)

2
asoc/codecs/wsa884x/wsa884x-regmap.c
View File

@@ -302,7 +302,7 @@ static struct reg_default wsa884x_defaults[] = {
{WSA884X_CLSH_VTH14, 0x00}, {WSA884X_CLSH_VTH14, 0x00},
{WSA884X_CLSH_VTH15, 0x00}, {WSA884X_CLSH_VTH15, 0x00},
{WSA884X_DIG_CTRL1_PAGE, 0x00}, {WSA884X_DIG_CTRL1_PAGE, 0x00},
{WSA884X_BST_CFG, 0x00}, {WSA884X_VPHX_SYS_EN_STATUS, 0x00},
{WSA884X_ANA_WO_CTL_0, 0xe9}, {WSA884X_ANA_WO_CTL_0, 0xe9},
{WSA884X_ANA_WO_CTL_1, 0x00}, {WSA884X_ANA_WO_CTL_1, 0x00},
{WSA884X_PIN_CTL, 0x04}, {WSA884X_PIN_CTL, 0x04},

2
asoc/codecs/wsa884x/wsa884x-tables.c
View File

@@ -299,7 +299,7 @@ const u8 wsa884x_reg_access[WSA884X_NUM_REGISTERS] = {
[WSA884X_REG(WSA884X_CLSH_VTH14)] = RD_WR_REG, [WSA884X_REG(WSA884X_CLSH_VTH14)] = RD_WR_REG,
[WSA884X_REG(WSA884X_CLSH_VTH15)] = RD_WR_REG, [WSA884X_REG(WSA884X_CLSH_VTH15)] = RD_WR_REG,
[WSA884X_REG(WSA884X_DIG_CTRL1_PAGE)] = RD_WR_REG, [WSA884X_REG(WSA884X_DIG_CTRL1_PAGE)] = RD_WR_REG,
[WSA884X_REG(WSA884X_BST_CFG)] = RD_REG, [WSA884X_REG(WSA884X_VPHX_SYS_EN_STATUS)] = RD_REG,
[WSA884X_REG(WSA884X_ANA_WO_CTL_0)] = RD_WR_REG, [WSA884X_REG(WSA884X_ANA_WO_CTL_0)] = RD_WR_REG,
[WSA884X_REG(WSA884X_ANA_WO_CTL_1)] = RD_WR_REG, [WSA884X_REG(WSA884X_ANA_WO_CTL_1)] = RD_WR_REG,
[WSA884X_REG(WSA884X_PIN_CTL)] = RD_WR_REG, [WSA884X_REG(WSA884X_PIN_CTL)] = RD_WR_REG,

66
asoc/codecs/wsa884x/wsa884x.c
View File

@@ -53,15 +53,8 @@
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
#define REG_FIELD_VALUE(register_name, field_name, value) \ #define REG_FIELD_VALUE(register_name, field_name, value) \
(WSA884X_##register_name, FIELD_MASK(register_name, field_name), \ WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
value << FIELD_SHIFT(register_name, field_name)) value << FIELD_SHIFT(register_name, field_name)
enum {
WSA_4OHMS = 4,
WSA_8OHMS = 8,
WSA_16OHMS = 16,
WSA_32OHMS = 32,
};
struct wsa_temp_register { struct wsa_temp_register {
u8 d1_msb; u8 d1_msb;
@@ -87,24 +80,16 @@ struct wsa_reg_mask_val {
}; };
static const struct wsa_reg_mask_val reg_init[] = { static const struct wsa_reg_mask_val reg_init[] = {
{REG_FIELD_VALUE(PA_FSM_BYP_CTL, PA_FSM_BYP, 0x00)},
{REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, 0x02)},
{REG_FIELD_VALUE(ADC_6, INTRLV_RST_OVRD, 0x01)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A4_1, COEF_A4, 0x02)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A5_1, COEF_A5, 0x02)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
{REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)}, {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
{REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)}, {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
{REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)}, {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
{REG_FIELD_VALUE(CDC_SPK_DSM_C_1, COEF_C5, 0x05)},
{REG_FIELD_VALUE(CDC_SPK_DSM_C_1, COEF_C4, 0x04)},
{REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)}, {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
{REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)}, {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
{REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)}, {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
@@ -114,33 +99,15 @@ static const struct wsa_reg_mask_val reg_init[] = {
{REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)}, {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
{REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)}, {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
{REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)}, {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
{REG_FIELD_VALUE(VBAT_SNS, BOP_FREQ, 0x01)}, {REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x00)},
{REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x09)}, {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
{REG_FIELD_VALUE(DRE_IDLE_DET_CTL, DRE_IDLE_FORCE_EN, 0x00)}, {REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, 0x0E)},
{REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x08)}, {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
{REG_FIELD_VALUE(DRE_CTL_0, OFFSET, 0x02)}, {REG_FIELD_VALUE(CLSH_VTH1, CLSH_VTH1, 0xFF)},
{REG_FIELD_VALUE(VAGC_TIME, REL_TIME, 0x03)}, {REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, 0x04)},
{REG_FIELD_VALUE(VAGC_TIME, HLD_TIME, 0x03)},
{REG_FIELD_VALUE(VAGC_ATTN_LVL_2, VBAT_ATTN_LVL, 0x01)},
{REG_FIELD_VALUE(VAGC_ATTN_LVL_3, VBAT_ATTN_LVL, 0x02)},
{REG_FIELD_VALUE(VAGC_CTL, VBAT_AGC_EN, 0x01)},
{REG_FIELD_VALUE(TAGC_CTL, THERMAL_THRESH, 0x05)},
{REG_FIELD_VALUE(TAGC_TIME, REL_TIME, 0x03)},
// {WSA884X_TAGC_E2E_GAIN, 0x1F, 0x02},???
{REG_FIELD_VALUE(TEMP_CONFIG0, CTL_THRD_SAF2WAR, 0x02)},
{REG_FIELD_VALUE(TEMP_CONFIG1, CTL_THRD_WAR2SAF, 0x02)},
{REG_FIELD_VALUE(OTP_REG_1, LOW_TEMP_MSB, 0x49)},
{REG_FIELD_VALUE(OTP_REG_2, LOW_TEMP_LSB, 0x02)},
{REG_FIELD_VALUE(OTP_REG_3, HIGH_TEMP_MSB, 0xC9)},
{REG_FIELD_VALUE(OTP_REG_4, HIGH_TEMP_LSB, 0x01)},
{REG_FIELD_VALUE(TAGC_CTL, THERMAL_AGC_EN, 0x01)},
{REG_FIELD_VALUE(ADC_2, ISNS_LOAD_STORED, 0x00)}, {REG_FIELD_VALUE(ADC_2, ISNS_LOAD_STORED, 0x00)},
{REG_FIELD_VALUE(ADC_7, EN_AZ_REG, 0x01)}, {REG_FIELD_VALUE(ADC_7, EN_AZ_REG, 0x01)},
{REG_FIELD_VALUE(ADC_7, EN_SAR_REG, 0x01)}, {REG_FIELD_VALUE(ADC_7, EN_SAR_REG, 0x01)}
{REG_FIELD_VALUE(CKWD_CTL_0, CKWD_FDIV_SEL, 0x00)},
{REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, 0x10)},
{REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x1B)},
{REG_FIELD_VALUE(BOOST_MISC, SPKR_RDY_CTL, 0x03)},
}; };
static int wsa884x_handle_post_irq(void *data); static int wsa884x_handle_post_irq(void *data);
@@ -148,9 +115,8 @@ static int wsa884x_get_temperature(struct snd_soc_component *component,
int *temp); int *temp);
enum { enum {
WSA8840 = 0, WSA8840 = 0,
WSA8845, WSA8845 = 5,
WSA8842, WSA884H = 12,
WSA8845_V2 = 5,
}; };
enum { enum {
@@ -674,9 +640,6 @@ static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
case WSA884X_VERSION_1_0: case WSA884X_VERSION_1_0:
len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n"); len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
break; break;
case WSA884X_VERSION_1_1:
len = snprintf(buffer, sizeof(buffer), "WSA884X_1_1\n");
break;
default: default:
len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
break; break;
@@ -710,11 +673,10 @@ static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
len = snprintf(buffer, sizeof(buffer), "WSA8840\n"); len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
break; break;
case WSA8845: case WSA8845:
case WSA8845_V2:
len = snprintf(buffer, sizeof(buffer), "WSA8845\n"); len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
break; break;
case WSA8842: case WSA884H:
len = snprintf(buffer, sizeof(buffer), "WSA8842\n"); len = snprintf(buffer, sizeof(buffer), "WSA884H\n");
break; break;
default: default:
len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n"); len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
@@ -1214,7 +1176,7 @@ static void wsa884x_codec_init(struct snd_soc_component *component)
snd_soc_component_update_bits(component, reg_init[i].reg, snd_soc_component_update_bits(component, reg_init[i].reg,
reg_init[i].mask, reg_init[i].val); reg_init[i].mask, reg_init[i].val);
if (wsa884x->variant == WSA8840 || wsa884x->variant == WSA8842) { if (wsa884x->variant == WSA8840 || wsa884x->variant == WSA8845) {
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
REG_FIELD_VALUE(DRE_CTL_0, OFFSET, 0x03)); REG_FIELD_VALUE(DRE_CTL_0, OFFSET, 0x03));
wsa884x->comp_offset = COMP_OFFSET3; wsa884x->comp_offset = COMP_OFFSET3;