asoc: codecs: Update register initialization sequence
Add latest register sequence. Remove version 1_2. Update header files with latest registers. Change-Id: I92f56e5ec2be4e695d42cec8610b9b9300410b02 Signed-off-by: Matthew Rice <mrice@codeaurora.org>
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Matthew Rice
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Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
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179ce4f13f
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@@ -9,79 +9,137 @@
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#include <linux/device.h>
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#include "wsa884x-registers.h"
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/*
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* Use in conjunction with wsa884x-reg-masks.c for field values.
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* field_value = (register_value & field_mask) >> field_shift
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*/
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#define FIELD_SHIFT(register_name, field_name) \
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WSA884X_##register_name##_##field_name##_SHIFT
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#define WSA884X_VBAT_SNS_BOP_FREQ_SHIFT 0x05
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#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 0x05
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#define WSA884X_ADC_2_ISNS_LOAD_STORED_SHIFT 0x06
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#define WSA884X_ADC_6_INTRLV_RST_OVRD_SHIFT 0x01
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#define WSA884X_ADC_7_EN_AZ_REG_SHIFT 0x02
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#define WSA884X_ADC_7_EN_SAR_REG_SHIFT 0x01
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#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 0x07
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#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 0x02
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#define WSA884X_BOOST_MISC_SPKR_RDY_CTL_SHIFT 0x05
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#define WSA884X_CKWD_CTL_0_CKWD_FDIV_SEL_SHIFT 0x05
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#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0x00
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#define WSA884X_CHIP_ID0_BYTE_0_SHIFT 0x00
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#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0x00
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#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_SHIFT 0x00
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#define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 0x07
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#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 0x06
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#define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 0x05
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#define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 0x02
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#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 0x01
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#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0x00
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#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0x00
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#define WSA884X_TEMP_CONFIG0_CTL_THRD_SAF2WAR_SHIFT 0x00
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#define WSA884X_TEMP_CONFIG1_CTL_THRD_WAR2SAF_SHIFT 0x00
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#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 0x01
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#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A4_1_COEF_A4_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A5_1_COEF_A5_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 0x04
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#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_C_1_COEF_C5_SHIFT 0x04
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#define WSA884X_CDC_SPK_DSM_C_1_COEF_C4_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 0x04
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#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_SHIFT 0x00
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#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_SHIFT 0x00
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#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0x00
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#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 0x04
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#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0x00
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#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 0x01
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#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0x00
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#define WSA884X_TAGC_CTL_THERMAL_THRESH_SHIFT 0x01
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#define WSA884X_TAGC_CTL_THERMAL_AGC_EN_SHIFT 0x00
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#define WSA884X_TAGC_TIME_REL_TIME_SHIFT 0x04
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#define WSA884X_VAGC_CTL_VBAT_AGC_EN_SHIFT 0x00
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#define WSA884X_VAGC_TIME_REL_TIME_SHIFT 0x02
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#define WSA884X_VAGC_TIME_HLD_TIME_SHIFT 0x00
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#define WSA884X_VAGC_ATTN_LVL_2_VBAT_ATTN_LVL_SHIFT 0x00
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#define WSA884X_VAGC_ATTN_LVL_3_VBAT_ATTN_LVL_SHIFT 0x00
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#define WSA884X_OTP_REG_0_WSA884X_ID_SHIFT 0x00
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#define WSA884X_OTP_REG_1_LOW_TEMP_MSB_SHIFT 0x00
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#define WSA884X_OTP_REG_2_LOW_TEMP_LSB_SHIFT 0x06
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#define WSA884X_OTP_REG_3_HIGH_TEMP_MSB_SHIFT 0x00
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#define WSA884X_OTP_REG_4_HIGH_TEMP_LSB_SHIFT 0x06
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#define WSA884X_DRE_IDLE_DET_CTL_PA_OFF_FORCE_EN_SHIFT 0x06
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#define WSA884X_DRE_IDLE_DET_CTL_PDM_WD_FORCE_EN_SHIFT 0x05
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#define WSA884X_DRE_IDLE_DET_CTL_DRE_IDLE_FORCE_EN_SHIFT 0x04
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#define WSA884X_DRE_IDLE_DET_CTL_DRE_FORCE_VALUE_SHIFT 0x00
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/* WSA884X_VSENSE1 Fields: */
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#define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 0x05
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#define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_SHIFT 0x04
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#define WSA884X_VSENSE1_IDLE_MODE_CTL_SHIFT 0x02
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#define WSA884X_VSENSE1_VOCM_AMP_CTL_SHIFT 0x00
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/* WSA884X_ADC_2 Fields: */
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#define WSA884X_ADC_2_ATEST_SEL_CAL_REF_SHIFT 0x07
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#define WSA884X_ADC_2_ISNS_LOAD_STORED_SHIFT 0x06
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#define WSA884X_ADC_2_EN_DET_SHIFT 0x05
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#define WSA884X_ADC_2_EN_ATEST_REF_SHIFT 0x04
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#define WSA884X_ADC_2_EN_ATEST_INT_SHIFT 0x01
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#define WSA884X_ADC_2_D_ADC_REG_EN_SHIFT 0x00
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/* WSA884X_ADC_7 Fields: */
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#define WSA884X_ADC_7_CLAMPON_SHIFT 0x07
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#define WSA884X_ADC_7_CAL_LOOP_TRIM_SHIFT 0x04
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#define WSA884X_ADC_7_REG_TRIM_EN_SHIFT 0x03
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#define WSA884X_ADC_7_EN_AZ_REG_SHIFT 0x02
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#define WSA884X_ADC_7_EN_SAR_REG_SHIFT 0x01
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#define WSA884X_ADC_7_EN_SW_CURRENT_REG_SHIFT 0x00
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/* WSA884X_BOP_DEGLITCH_CTL Fields: */
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#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 0x01
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#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A2_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A2_1 Fields: */
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#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A3_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A3_1 Fields: */
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#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A4_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A5_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A6_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_A7_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_C_0 Fields: */
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#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 0x04
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#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_C_2 Fields: */
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#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 0x04
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#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_C_3 Fields: */
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#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R1 Fields: */
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#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R2 Fields: */
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#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R3 Fields: */
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#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R4 Fields: */
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#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R5 Fields: */
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#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R6 Fields: */
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#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_SHIFT 0x00
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/* WSA884X_CDC_SPK_DSM_R7 Fields: */
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#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_SHIFT 0x00
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/* WSA884X_DRE_CTL_0 Fields: */
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#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 0x04
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#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0x00
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/* WSA884X_GAIN_RAMPING_MIN Fields: */
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#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0x00
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/* WSA884X_CLSH_SOFT_MAX Fields: */
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#define WSA884X_CLSH_SOFT_MAX_SOFT_MAX_SHIFT 0x00
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/* WSA884X_CLSH_VTH1 Fields: */
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#define WSA884X_CLSH_VTH1_CLSH_VTH1_SHIFT 0x00
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/* WSA884X_CLSH_VTH10 Fields: */
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#define WSA884X_CLSH_VTH10_CLSH_VTH10_SHIFT 0x00
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/* WSA884X_CLSH_VTH11 Fields: */
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#define WSA884X_CLSH_VTH11_CLSH_VTH11_SHIFT 0x00
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/* WSA884X_CLSH_VTH12 Fields: */
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#define WSA884X_CLSH_VTH12_CLSH_VTH12_SHIFT 0x00
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/* WSA884X_CLSH_VTH13 Fields: */
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#define WSA884X_CLSH_VTH13_CLSH_VTH13_SHIFT 0x00
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/* WSA884X_CLSH_VTH14 Fields: */
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#define WSA884X_CLSH_VTH14_CLSH_VTH14_SHIFT 0x00
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/* WSA884X_CLSH_VTH15 Fields: */
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#define WSA884X_CLSH_VTH15_CLSH_VTH15_SHIFT 0x00
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/* WSA884X_ANA_WO_CTL_0 Fields: */
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#define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_SHIFT 0x06
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#define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_SHIFT 0x02
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#define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_SHIFT 0x01
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#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_SHIFT 0x00
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/* WSA884X_ANA_WO_CTL_1 Fields: */
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#define WSA884X_ANA_WO_CTL_1_BOOST_SHARE_EN_SHIFT 0x03
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#define WSA884X_ANA_WO_CTL_1_EXT_VDDSPK_EN_SHIFT 0x00
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/* WSA884X_DRE_CTL_1 Fields: */
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#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 0x01
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#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0x00
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/* WSA884X_VBAT_THRM_FLT_CTL Fields: */
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#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 0x05
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#define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 0x04
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#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 0x01
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#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0x00
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/* WSA884X_PDM_WD_CTL Fields: */
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#define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 0x02
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#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 0x01
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#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0x00
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/* WSA884X_PA_FSM_BYP_CTL Fields: */
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#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_SHIFT 0x00
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/* WSA884X_TADC_VALUE_CTL Fields: */
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#define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_SHIFT 0x01
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#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0x00
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/* WSA884X_PA_FSM_BYP0 Fields: */
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#define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 0x07
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#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 0x06
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#define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 0x05
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#define WSA884X_PA_FSM_BYP0_PA_EN_SHIFT 0x04
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#define WSA884X_PA_FSM_BYP0_BOOST_EN_SHIFT 0x03
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#define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 0x02
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#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 0x01
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#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0x00
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/* WSA884X_PA_FSM_BYP1 Fields: */
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#define WSA884X_PA_FSM_BYP1_NG_MODE_SHIFT 0x06
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#define WSA884X_PA_FSM_BYP1_PWRSAV_CTL_SHIFT 0x05
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#define WSA884X_PA_FSM_BYP1_RAMP_DOWN_SHIFT 0x04
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#define WSA884X_PA_FSM_BYP1_RAMP_UP_SHIFT 0x03
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#define WSA884X_PA_FSM_BYP1_BLEEDER_EN_SHIFT 0x02
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#define WSA884X_PA_FSM_BYP1_PA_MAIN_EN_SHIFT 0x01
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#define WSA884X_PA_FSM_BYP1_PA_AUX_EN_SHIFT 0x00
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/* WSA884X_PA_FSM_EN Fields: */
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#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0x00
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#endif /* WSA884X_REG_SHIFTS_H */
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