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@@ -1011,7 +1011,6 @@ irqreturn_t cam_csiphy_irq(int irq_num, void *data)
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{
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struct csiphy_device *csiphy_dev =
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(struct csiphy_device *)data;
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- struct cam_hw_soc_info *soc_info = NULL;
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struct csiphy_reg_parms_t *csiphy_reg = NULL;
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void __iomem *base = NULL;
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@@ -1020,7 +1019,6 @@ irqreturn_t cam_csiphy_irq(int irq_num, void *data)
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return IRQ_NONE;
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}
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- soc_info = &csiphy_dev->soc_info;
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base = csiphy_dev->soc_info.reg_map[0].mem_base;
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csiphy_reg = csiphy_dev->ctrl_reg->csiphy_reg;
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@@ -1273,9 +1271,6 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
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int32_t rc = 0;
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uint32_t lane_enable = 0;
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uint16_t i = 0, cfg_size = 0;
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- uint16_t lane_assign = 0;
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- uint8_t lane_cnt;
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- int max_lanes = 0;
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uint16_t settle_cnt = 0;
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uint8_t skew_cal_enable = 0;
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uint64_t intermediate_var;
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@@ -1320,7 +1315,6 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
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reg_array = csiphy_dev->ctrl_reg->csiphy_3ph_reg;
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cfg_size = csiphy_reg->csiphy_3ph_config_array_size;
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}
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- max_lanes = CAM_CSIPHY_MAX_CPHY_LANES;
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} else {
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/* DPHY combo mode*/
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if (csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg) {
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@@ -1332,20 +1326,17 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
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cfg_size = csiphy_reg->csiphy_2ph_config_array_size;
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}
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- max_lanes = MAX_LANES;
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}
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} else if (csiphy_dev->cphy_dphy_combo_mode) {
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/* for CPHY and DPHY combo mode selection */
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if (csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg) {
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reg_array = csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg;
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cfg_size = csiphy_reg->csiphy_2ph_3ph_config_array_size;
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- max_lanes = CAM_CSIPHY_MAX_CPHY_DPHY_COMBO_LN;
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} else {
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reg_array = csiphy_dev->ctrl_reg->csiphy_3ph_reg;
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cfg_size = csiphy_reg->csiphy_3ph_config_array_size;
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CAM_WARN(CAM_CSIPHY,
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"Unsupported configuration, Falling back to CPHY mission mode");
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- max_lanes = CAM_CSIPHY_MAX_CPHY_LANES;
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}
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} else {
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/* for CPHY(3Phase) or DPHY(2Phase) Non combe mode selection */
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@@ -1353,19 +1344,15 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
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CAM_DBG(CAM_CSIPHY,
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"3phase Non combo mode reg array selected");
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reg_array = csiphy_dev->ctrl_reg->csiphy_3ph_reg;
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- max_lanes = CAM_CSIPHY_MAX_CPHY_LANES;
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cfg_size = csiphy_reg->csiphy_3ph_config_array_size;
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} else {
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CAM_DBG(CAM_CSIPHY,
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"2PHASE Non combo mode reg array selected");
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reg_array = csiphy_dev->ctrl_reg->csiphy_2ph_reg;
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cfg_size = csiphy_reg->csiphy_2ph_config_array_size;
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- max_lanes = MAX_LANES;
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}
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}
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- lane_cnt = csiphy_dev->csiphy_info[index].lane_cnt;
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- lane_assign = csiphy_dev->csiphy_info[index].lane_assign;
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lane_enable = csiphy_dev->csiphy_info[index].lane_enable;
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@@ -1423,7 +1410,6 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
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void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev)
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{
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struct cam_hw_soc_info *soc_info;
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- struct csiphy_reg_parms_t *csiphy_reg;
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struct cam_csiphy_param *param;
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int32_t i = 0;
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int rc = 0;
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@@ -1441,8 +1427,6 @@ void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev)
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CSIPHY_MAX_INSTANCES_PER_PHY;
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}
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- csiphy_reg = csiphy_dev->ctrl_reg->csiphy_reg;
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-
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if ((csiphy_dev->csiphy_state == CAM_CSIPHY_START) ||
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csiphy_dev->start_dev_count) {
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soc_info = &csiphy_dev->soc_info;
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@@ -1663,7 +1647,6 @@ int cam_csiphy_util_update_aon_registration(uint32_t phy_idx, uint32_t aon_cam_i
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int cam_csiphy_util_update_aon_ops(
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bool get_access, uint32_t phy_idx)
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{
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- uint32_t cpas_hdl = 0;
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struct cam_csiphy_aon_sel_params_t *aon_sel_params;
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int rc = 0;
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@@ -1682,7 +1665,6 @@ int cam_csiphy_util_update_aon_ops(
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return -EINVAL;
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}
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- cpas_hdl = g_phy_data[phy_idx].cpas_handle;
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aon_sel_params = g_phy_data[phy_idx].aon_sel_param;
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mutex_lock(&main_aon_selection);
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