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qcacmn: Enable napi to re-enable interrupts

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When NAPI is busy processing Rx, interrupt is not re-enabled
and this causes CE2 and other pipes to become full and target asserts.
This patch enables napi to return after processing half of the descriptors.

Change-Id: I2ba443c388f1a9d36331c632bfb2fbbbe876228f
Crs-fixed: 1094034
This commit is contained in:
Nandha Kishore Easwaran
2016-11-24 13:31:19 +05:30
committed by qcabuildsw
parent d1141c298f
commit cbff9c9090
4 changed files with 25 additions and 2 deletions
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10
hif/src/ce/ce_service.c
View File

@@ -198,6 +198,14 @@ inline void ce_init_ce_desc_event_log(int ce_id, int size)
} }
#endif #endif
#ifdef NAPI_YIELD_BUDGET_BASED
bool hif_ce_service_should_yield(struct hif_softc *scn,
struct CE_state *ce_state)
{
bool yield = hif_max_num_receives_reached(scn, ce_state->receive_count);
return yield;
}
#else
/** /**
* hif_ce_service_should_yield() - return true if the service is hogging the cpu * hif_ce_service_should_yield() - return true if the service is hogging the cpu
* @scn: hif context * @scn: hif context
@@ -213,7 +221,7 @@ bool hif_ce_service_should_yield(struct hif_softc *scn,
hif_max_num_receives_reached(scn, ce_state->receive_count); hif_max_num_receives_reached(scn, ce_state->receive_count);
return yield; return yield;
} }
#endif
/* /*
* Support for Copy Engine hardware, which is mainly used for * Support for Copy Engine hardware, which is mainly used for
* communication between Host and Target over a PCIe interconnect. * communication between Host and Target over a PCIe interconnect.

10
hif/src/hif_main.c
View File

@@ -196,6 +196,15 @@ uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset)
} }
} }
#ifdef NAPI_YIELD_BUDGET_BASED
bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count)
{
if (QDF_IS_EPPING_ENABLED(hif_get_conparam(scn)))
return count > 120;
else
return count > MAX_REAP_COUNT_PER_NAPI_POLL;
}
#else
/** /**
* hif_max_num_receives_reached() - check max receive is reached * hif_max_num_receives_reached() - check max receive is reached
* @scn: HIF Context * @scn: HIF Context
@@ -212,6 +221,7 @@ bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count)
else else
return count > MAX_NUM_OF_RECEIVES; return count > MAX_NUM_OF_RECEIVES;
} }
#endif
/** /**
* init_buffer_count() - initial buffer count * init_buffer_count() - initial buffer count

2
hif/src/hif_main.h
View File

@@ -66,6 +66,8 @@
#define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES
#define MAX_REAP_COUNT_PER_NAPI_POLL 256
#ifdef QCA_WIFI_3_0_ADRASTEA #ifdef QCA_WIFI_3_0_ADRASTEA
#define ADRASTEA_BU 1 #define ADRASTEA_BU 1
#else #else

5
hif/src/hif_napi.c
View File

@@ -761,8 +761,11 @@ int hif_napi_poll(struct hif_opaque_softc *hif_ctx, struct napi_struct *napi,
if (0 == rc) if (0 == rc)
NAPI_DEBUG("%s:%d: nothing processed by CE. Completing NAPI", NAPI_DEBUG("%s:%d: nothing processed by CE. Completing NAPI",
__func__, __LINE__); __func__, __LINE__);
#ifdef NAPI_YIELD_BUDGET_BASED
if (ce_state && (ce_state->force_break || 0 == rc)) {
#else
if (ce_state && (!ce_check_rx_pending(ce_state) || 0 == rc)) { if (ce_state && (!ce_check_rx_pending(ce_state) || 0 == rc)) {
#endif
napi_info->stats[cpu].napi_completes++; napi_info->stats[cpu].napi_completes++;
hif_record_ce_desc_event(hif, ce_state->id, NAPI_COMPLETE, hif_record_ce_desc_event(hif, ce_state->id, NAPI_COMPLETE,