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qcacmn: Add debug to print the Interrupt enable registers

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These are currently enabled only for WIN ahb platforms

Change-Id: Ibd68d5625b6cf790097111c15aece31ea52c0324
CRs-Fixed: 3153652
This commit is contained in:
Vinay Adella
2022-04-18 14:34:27 +05:30
committed by Madan Koyyalamudi
parent e7861fb758
commit cbb1a0ec9b
1 changed files with 34 additions and 0 deletions
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34
hif/src/snoc/if_ahb.c
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@@ -747,12 +747,46 @@ bool hif_ahb_needs_bmi(struct hif_softc *scn)
return !ce_srng_based(scn);
}
/**
* hif_display_ahb_irq_regs() - prints the host interrupt enable (IE) regs
* @scn: hif context
*
* Return: None
*/
void hif_display_ahb_irq_regs(struct hif_softc *scn)
{
uint32_t regval;
void *mem = scn->mem_ce ? scn->mem_ce : scn->mem;
struct hif_target_info *tgt_info = &scn->target_info;
if (scn->per_ce_irq) {
regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS);
hif_nofl_err("IRQ enable register value 0x%08x", regval);
regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS_2);
hif_nofl_err("IRQ enable register 2 value 0x%08x", regval);
if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
tgt_info->target_type == TARGET_TYPE_QCA9574 ||
tgt_info->target_type == TARGET_TYPE_QCA5018 ||
tgt_info->target_type == TARGET_TYPE_QCA6018) {
regval = hif_read32_mb(scn, mem +
HOST_IE_ADDRESS_3);
hif_nofl_err("IRQ enable register 3 value 0x%08x",
regval);
}
}
}
void hif_ahb_display_stats(struct hif_softc *scn)
{
if (!scn) {
hif_err("hif_scn null");
return;
}
hif_display_ahb_irq_regs(scn);
hif_display_ce_stats(scn);
}