diff --git a/driver/platform/anorak/src/msm_vidc_anorak.c b/driver/platform/anorak/src/msm_vidc_anorak.c index 9b9308112d..32f9c5d943 100644 --- a/driver/platform/anorak/src/msm_vidc_anorak.c +++ b/driver/platform/anorak/src/msm_vidc_anorak.c @@ -4,8 +4,13 @@ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + +#include #include +#include #include "msm_vidc_anorak.h" #include "msm_vidc_platform.h" #include "msm_vidc_debug.h" @@ -81,7 +86,6 @@ static struct msm_platform_core_capability core_data_anorak[] = { {AV_SYNC_WINDOW_SIZE, 40}, {NON_FATAL_FAULTS, 1}, {ENC_AUTO_FRAMERATE, 1}, - {MMRM, 0}, {DEVICE_CAPS, V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING}, {SUPPORTS_REQUESTS, 1}, @@ -2415,7 +2419,84 @@ static struct msm_vidc_ubwc_config_data ubwc_config_anorak[] = { UBWC_CONFIG(8, 32, 16, 0, 1, 1, 1), }; +/* name, min_kbps, max_kbps */ +static const struct bw_table anorak_bw_table[] = { + { "venus-cnoc", 1000, 1000 }, + { "venus-ddr", 1000, 15000000 }, + { "venus-llcc", 1000, 15000000 }, +}; + +/* name, hw_trigger */ +static const struct regulator_table anorak_regulator_table[] = { + { "iris-ctl", 0 }, + { "vcodec", 1 }, +}; + +/* name, clock id, scaling */ +static const struct clk_table anorak_clk_table[] = { + { "gcc_video_axi0", GCC_VIDEO_AXI0_CLK, 0 }, + { "core_clk", VIDEO_CC_MVS0C_CLK, 0 }, + { "vcodec_clk", VIDEO_CC_MVS0_CLK, 0 }, + { "video_cc_mvs0_clk_src", VIDEO_CC_MVS0_CLK_SRC, 1 }, +}; + +/* name */ +static const struct clk_rst_table anorak_clk_reset_table[] = { + { "video_axi_reset" }, +}; + +/* name, llcc_id */ +static const struct subcache_table anorak_subcache_table[] = { + { "vidsc0", LLCC_VIDSC0 }, + { "vidvsp", LLCC_VIDVSP }, +}; + +/* name, start, size, secure, dma_coherant, region */ +const struct context_bank_table anorak_context_bank_table[] = { + {"qcom,vidc,cb-ns", 0x25800000, 0xba800000, 0, 1, MSM_VIDC_NON_SECURE }, + {"qcom,vidc,cb-ns-pxl", 0x00100000, 0xdff00000, 0, 1, MSM_VIDC_NON_SECURE_PIXEL }, + {"qcom,vidc,cb-sec-pxl", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_PIXEL }, + {"qcom,vidc,cb-sec-non-pxl", 0x01000000, 0x24800000, 1, 0, MSM_VIDC_SECURE_NONPIXEL }, + {"qcom,vidc,cb-sec-bitstream", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_BITSTREAM }, +}; + +/* freq */ +static struct freq_table anorak_freq_table[] = { + {533000000}, {444000000}, {366000000}, {338000000}, {240000000} +}; + +/* register, value, mask */ +static const struct reg_preset_table anorak_reg_preset_table[] = { + { 0xB0088, 0x0, 0x11 }, +}; + static const struct msm_vidc_platform_data anorak_data = { + /* resources dependent on other module */ + .bw_tbl = anorak_bw_table, + .bw_tbl_size = ARRAY_SIZE(anorak_bw_table), + .regulator_tbl = anorak_regulator_table, + .regulator_tbl_size = ARRAY_SIZE(anorak_regulator_table), + .clk_tbl = anorak_clk_table, + .clk_tbl_size = ARRAY_SIZE(anorak_clk_table), + .clk_rst_tbl = anorak_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(anorak_clk_reset_table), + .subcache_tbl = anorak_subcache_table, + .subcache_tbl_size = ARRAY_SIZE(anorak_subcache_table), + + /* populate context bank */ + .context_bank_tbl = anorak_context_bank_table, + .context_bank_tbl_size = ARRAY_SIZE(anorak_context_bank_table), + + /* platform specific resources */ + .freq_tbl = anorak_freq_table, + .freq_tbl_size = ARRAY_SIZE(anorak_freq_table), + .reg_prst_tbl = anorak_reg_preset_table, + .reg_prst_tbl_size = ARRAY_SIZE(anorak_reg_preset_table), + .fwname = "vpu33_4v", + .pas_id = 9, + .supports_mmrm = 0, + + /* caps related resorces */ .core_data = core_data_anorak, .core_data_size = ARRAY_SIZE(core_data_anorak), .inst_cap_data = instance_cap_data_anorak, diff --git a/driver/platform/pineapple/src/msm_vidc_pineapple.c b/driver/platform/pineapple/src/msm_vidc_pineapple.c index 64a63df395..bf86f88a97 100644 --- a/driver/platform/pineapple/src/msm_vidc_pineapple.c +++ b/driver/platform/pineapple/src/msm_vidc_pineapple.c @@ -4,6 +4,10 @@ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + +#include #include #include @@ -315,7 +319,6 @@ static struct msm_platform_core_capability core_data_pineapple[] = { {AV_SYNC_WINDOW_SIZE, 40}, {NON_FATAL_FAULTS, 1}, {ENC_AUTO_FRAMERATE, 1}, - {MMRM, 1}, {DEVICE_CAPS, V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING}, {SUPPORTS_REQUESTS, 1}, @@ -2626,7 +2629,84 @@ static struct msm_vidc_format_capability format_data_pineapple = { .matrix_coeff_info_size = ARRAY_SIZE(matrix_coeff_data_pineapple), }; +/* name, min_kbps, max_kbps */ +static const struct bw_table pineapple_bw_table[] = { + { "venus-cnoc", 1000, 1000 }, + { "venus-ddr", 1000, 15000000 }, + { "venus-llcc", 1000, 15000000 }, +}; + +/* name, hw_trigger */ +static const struct regulator_table pineapple_regulator_table[] = { + { "iris-ctl", 0 }, + { "vcodec", 1 }, +}; + +/* name, clock id, scaling */ +static const struct clk_table pineapple_clk_table[] = { + { "gcc_video_axi0", GCC_VIDEO_AXI0_CLK, 0 }, + { "core_clk", VIDEO_CC_MVS0C_CLK, 0 }, + { "vcodec_clk", VIDEO_CC_MVS0_CLK, 0 }, + { "video_cc_mvs0_clk_src", VIDEO_CC_MVS0_CLK_SRC, 1 }, +}; + +/* name */ +static const struct clk_rst_table pineapple_clk_reset_table[] = { + { "video_axi_reset" }, + { "video_core_reset" }, +}; + +/* name, llcc_id */ +static const struct subcache_table pineapple_subcache_table[] = { + { "vidsc0", LLCC_VIDSC0 }, +}; + +/* name, start, size, secure, dma_coherant */ +const struct context_bank_table pineapple_context_bank_table[] = { + {"qcom,vidc,cb-ns", 0x25800000, 0xba800000, 0, 1, MSM_VIDC_NON_SECURE }, + {"qcom,vidc,cb-ns-pxl", 0x00100000, 0xdff00000, 0, 1, MSM_VIDC_NON_SECURE_PIXEL }, + {"qcom,vidc,cb-sec-pxl", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_PIXEL }, + {"qcom,vidc,cb-sec-non-pxl", 0x01000000, 0x24800000, 1, 0, MSM_VIDC_SECURE_NONPIXEL }, + {"qcom,vidc,cb-sec-bitstream", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_BITSTREAM }, +}; + +/* freq */ +static struct freq_table pineapple_freq_table[] = { + {480000000}, {435000000}, {380000000}, {280000000} +}; + +/* register, value, mask */ +static const struct reg_preset_table pineapple_reg_preset_table[] = { + { 0xB0088, 0x0, 0x11 }, +}; + static const struct msm_vidc_platform_data pineapple_data = { + /* resources dependent on other module */ + .bw_tbl = pineapple_bw_table, + .bw_tbl_size = ARRAY_SIZE(pineapple_bw_table), + .regulator_tbl = pineapple_regulator_table, + .regulator_tbl_size = ARRAY_SIZE(pineapple_regulator_table), + .clk_tbl = pineapple_clk_table, + .clk_tbl_size = ARRAY_SIZE(pineapple_clk_table), + .clk_rst_tbl = pineapple_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(pineapple_clk_reset_table), + .subcache_tbl = pineapple_subcache_table, + .subcache_tbl_size = ARRAY_SIZE(pineapple_subcache_table), + + /* populate context bank */ + .context_bank_tbl = pineapple_context_bank_table, + .context_bank_tbl_size = ARRAY_SIZE(pineapple_context_bank_table), + + /* platform specific resources */ + .freq_tbl = pineapple_freq_table, + .freq_tbl_size = ARRAY_SIZE(pineapple_freq_table), + .reg_prst_tbl = pineapple_reg_preset_table, + .reg_prst_tbl_size = ARRAY_SIZE(pineapple_reg_preset_table), + .fwname = "vpu33_4v", + .pas_id = 9, + .supports_mmrm = 0, + + /* caps related resorces */ .core_data = core_data_pineapple, .core_data_size = ARRAY_SIZE(core_data_pineapple), .inst_cap_data = instance_cap_data_pineapple, diff --git a/driver/platform/waipio/inc/msm_vidc_waipio.h b/driver/platform/waipio/inc/msm_vidc_waipio.h index bfea9a97e3..c40fcde3cb 100644 --- a/driver/platform/waipio/inc/msm_vidc_waipio.h +++ b/driver/platform/waipio/inc/msm_vidc_waipio.h @@ -12,9 +12,16 @@ #endif #if defined(CONFIG_MSM_VIDC_WAIPIO) +struct context_bank_info *msm_vidc_context_bank(struct msm_vidc_core *core, + enum msm_vidc_buffer_region region); int msm_vidc_init_platform_waipio(struct msm_vidc_core *core, struct device *dev); int msm_vidc_deinit_platform_waipio(struct msm_vidc_core *core, struct device *dev); #else +struct context_bank_info *msm_vidc_context_bank(struct msm_vidc_core *core, + enum msm_vidc_buffer_region region) +{ + return NULL; +} int msm_vidc_init_platform_waipio(struct msm_vidc_core *core, struct device *dev) { return -EINVAL; diff --git a/driver/platform/waipio/src/msm_vidc_waipio.c b/driver/platform/waipio/src/msm_vidc_waipio.c index 607fe37ba0..b4257de3b5 100644 --- a/driver/platform/waipio/src/msm_vidc_waipio.c +++ b/driver/platform/waipio/src/msm_vidc_waipio.c @@ -4,8 +4,13 @@ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ -#include +#include +#include +#include +#include + +#include #include "msm_vidc_waipio.h" #include "msm_vidc_platform.h" #include "msm_vidc_debug.h" @@ -78,7 +83,6 @@ static struct msm_platform_core_capability core_data_waipio[] = { {AV_SYNC_WINDOW_SIZE, 40}, {NON_FATAL_FAULTS, 1}, {ENC_AUTO_FRAMERATE, 1}, - {MMRM, 1}, {DEVICE_CAPS, V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING}, {SUPPORTS_REQUESTS, 1}, @@ -2169,7 +2173,84 @@ static struct msm_vidc_ubwc_config_data ubwc_config_waipio[] = { UBWC_CONFIG(8, 32, 16, 0, 1, 1, 1), }; +/* name, min_kbps, max_kbps */ +static const struct bw_table waipio_bw_table[] = { + { "venus-cnoc", 1000, 1000 }, + { "venus-ddr", 1000, 15000000 }, + { "venus-llcc", 1000, 15000000 }, +}; + +/* name, hw_trigger */ +static const struct regulator_table waipio_regulator_table[] = { + { "iris-ctl", 0 }, + { "vcodec", 1 }, +}; + +/* name, clock id, scaling */ +static const struct clk_table waipio_clk_table[] = { + { "gcc_video_axi0", GCC_VIDEO_AXI0_CLK, 0 }, + { "core_clk", VIDEO_CC_MVS0C_CLK, 0 }, + { "vcodec_clk", VIDEO_CC_MVS0_CLK, 0 }, + { "video_cc_mvs0_clk_src", VIDEO_CC_MVS0_CLK_SRC, 1 }, +}; + +/* name */ +static const struct clk_rst_table waipio_clk_reset_table[] = { + { "video_axi_reset" }, + { "video_core_reset" }, +}; + +/* name, llcc_id */ +static const struct subcache_table waipio_subcache_table[] = { + { "vidsc0", LLCC_VIDSC0 }, +}; + +/* name, start, size, secure, dma_coherant */ +const struct context_bank_table waipio_context_bank_table[] = { + {"qcom,vidc,cb-ns", 0x25800000, 0xba800000, 0, 1, MSM_VIDC_NON_SECURE }, + {"qcom,vidc,cb-ns-pxl", 0x00100000, 0xdff00000, 0, 1, MSM_VIDC_NON_SECURE_PIXEL }, + {"qcom,vidc,cb-sec-pxl", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_PIXEL }, + {"qcom,vidc,cb-sec-non-pxl", 0x01000000, 0x24800000, 1, 0, MSM_VIDC_SECURE_NONPIXEL }, + {"qcom,vidc,cb-sec-bitstream", 0x00500000, 0xdfb00000, 1, 0, MSM_VIDC_SECURE_BITSTREAM }, +}; + +/* freq */ +static struct freq_table waipio_freq_table[] = { + {444000000}, {366000000}, {338000000}, {239999999} +}; + +/* register, value, mask */ +static const struct reg_preset_table waipio_reg_preset_table[] = { + { 0xB0088, 0x0, 0x11 }, +}; + static const struct msm_vidc_platform_data waipio_data = { + /* resources dependent on other module */ + .bw_tbl = waipio_bw_table, + .bw_tbl_size = ARRAY_SIZE(waipio_bw_table), + .regulator_tbl = waipio_regulator_table, + .regulator_tbl_size = ARRAY_SIZE(waipio_regulator_table), + .clk_tbl = waipio_clk_table, + .clk_tbl_size = ARRAY_SIZE(waipio_clk_table), + .clk_rst_tbl = waipio_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(waipio_clk_reset_table), + .subcache_tbl = waipio_subcache_table, + .subcache_tbl_size = ARRAY_SIZE(waipio_subcache_table), + + /* populate context bank */ + .context_bank_tbl = waipio_context_bank_table, + .context_bank_tbl_size = ARRAY_SIZE(waipio_context_bank_table), + + /* platform specific resources */ + .freq_tbl = waipio_freq_table, + .freq_tbl_size = ARRAY_SIZE(waipio_freq_table), + .reg_prst_tbl = waipio_reg_preset_table, + .reg_prst_tbl_size = ARRAY_SIZE(waipio_reg_preset_table), + .fwname = "vpu20_4v", + .pas_id = 9, + .supports_mmrm = 0, + + /* caps related resorces */ .core_data = core_data_waipio, .core_data_size = ARRAY_SIZE(core_data_waipio), .inst_cap_data = instance_cap_data_waipio, diff --git a/driver/variant/iris2/src/msm_vidc_buffer_iris2.c b/driver/variant/iris2/src/msm_vidc_buffer_iris2.c index bae3504453..639f136f39 100644 --- a/driver/variant/iris2/src/msm_vidc_buffer_iris2.c +++ b/driver/variant/iris2/src/msm_vidc_buffer_iris2.c @@ -9,7 +9,6 @@ #include "msm_vidc_buffer.h" #include "msm_vidc_inst.h" #include "msm_vidc_core.h" -#include "msm_vidc_platform.h" #include "msm_vidc_driver.h" #include "msm_vidc_debug.h" #include "msm_media_info.h" @@ -203,7 +202,7 @@ static u32 msm_vidc_decoder_dpb_size_iris2(struct msm_vidc_inst *inst) { u32 size = 0; - u32 color_fmt, v4l2_fmt; + u32 color_fmt; u32 width, height; struct v4l2_format *f; diff --git a/driver/variant/iris2/src/msm_vidc_iris2.c b/driver/variant/iris2/src/msm_vidc_iris2.c index 51434d9d85..102b56346c 100644 --- a/driver/variant/iris2/src/msm_vidc_iris2.c +++ b/driver/variant/iris2/src/msm_vidc_iris2.c @@ -10,7 +10,6 @@ #include "msm_vidc_core.h" #include "msm_vidc_driver.h" #include "msm_vidc_control.h" -#include "msm_vidc_dt.h" #include "msm_vidc_internal.h" #include "msm_vidc_buffer.h" #include "msm_vidc_debug.h" @@ -442,7 +441,7 @@ static int __power_off_iris2(struct msm_vidc_core *core) d_vpr_e("%s: failed to unvote buses\n", __func__); if (!(core->intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2)) - disable_irq_nosync(core->dt->irq); + disable_irq_nosync(core->resource->irq); core->intr_status = 0; core->power_enabled = false; @@ -506,7 +505,7 @@ fail_regulator: static int __power_on_iris2(struct msm_vidc_core *core) { const struct msm_vidc_resources_ops *res_ops = core->res_ops; - struct allowed_clock_rates_table *clk_tbl; + struct frequency_table *freq_tbl; u32 freq = 0; int rc = 0; @@ -534,9 +533,9 @@ static int __power_on_iris2(struct msm_vidc_core *core) /* video controller and hardware powered on successfully */ core->power_enabled = true; - clk_tbl = core->dt->allowed_clks_tbl; + freq_tbl = core->resource->freq_set.freq_tbl; freq = core->power.clk_freq ? core->power.clk_freq : - clk_tbl[0].clock_rate; + freq_tbl[0].freq; rc = res_ops->set_clks(core, freq); if (rc) { @@ -554,7 +553,7 @@ static int __power_on_iris2(struct msm_vidc_core *core) __interrupt_init_iris2(core); core->intr_status = 0; - enable_irq(core->dt->irq); + enable_irq(core->resource->irq); return rc; diff --git a/driver/variant/iris2/src/msm_vidc_power_iris2.c b/driver/variant/iris2/src/msm_vidc_power_iris2.c index 6b33cfc2a3..badec882bf 100644 --- a/driver/variant/iris2/src/msm_vidc_power_iris2.c +++ b/driver/variant/iris2/src/msm_vidc_power_iris2.c @@ -8,7 +8,6 @@ #include "msm_vidc_core.h" #include "msm_vidc_driver.h" #include "msm_vidc_debug.h" -#include "msm_vidc_dt.h" u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size) { @@ -28,7 +27,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size) } core = inst->core; - if (!core->dt) { + if (!core->resource) { d_vpr_e("%s: invalid params\n", __func__); return freq; } diff --git a/driver/variant/iris33/src/msm_vidc_buffer_iris33.c b/driver/variant/iris33/src/msm_vidc_buffer_iris33.c index d1c95157b7..931fe85255 100644 --- a/driver/variant/iris33/src/msm_vidc_buffer_iris33.c +++ b/driver/variant/iris33/src/msm_vidc_buffer_iris33.c @@ -10,7 +10,6 @@ #include "msm_vidc_buffer.h" #include "msm_vidc_inst.h" #include "msm_vidc_core.h" -#include "msm_vidc_platform.h" #include "msm_vidc_driver.h" #include "msm_vidc_debug.h" #include "msm_media_info.h" diff --git a/driver/variant/iris33/src/msm_vidc_iris33.c b/driver/variant/iris33/src/msm_vidc_iris33.c index 5c8aeead12..0c01f43b09 100644 --- a/driver/variant/iris33/src/msm_vidc_iris33.c +++ b/driver/variant/iris33/src/msm_vidc_iris33.c @@ -12,7 +12,6 @@ #include "msm_vidc_core.h" #include "msm_vidc_driver.h" #include "msm_vidc_control.h" -#include "msm_vidc_dt.h" #include "msm_vidc_internal.h" #include "msm_vidc_buffer.h" #include "msm_vidc_debug.h" @@ -548,7 +547,7 @@ static int __power_off_iris33(struct msm_vidc_core *core) d_vpr_e("%s: failed to unvote buses\n", __func__); if (!(core->intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS33)) - disable_irq_nosync(core->dt->irq); + disable_irq_nosync(core->resource->irq); core->intr_status = 0; core->power_enabled = false; @@ -612,7 +611,7 @@ fail_regulator: static int __power_on_iris33(struct msm_vidc_core *core) { const struct msm_vidc_resources_ops *res_ops = core->res_ops; - struct allowed_clock_rates_table *clk_tbl; + struct frequency_table *freq_tbl; u32 freq = 0; int rc = 0; @@ -640,9 +639,9 @@ static int __power_on_iris33(struct msm_vidc_core *core) /* video controller and hardware powered on successfully */ core->power_enabled = true; - clk_tbl = core->dt->allowed_clks_tbl; + freq_tbl = core->resource->freq_set.freq_tbl; freq = core->power.clk_freq ? core->power.clk_freq : - clk_tbl[0].clock_rate; + freq_tbl[0].freq; rc = res_ops->set_clks(core, freq); if (rc) { @@ -657,7 +656,7 @@ static int __power_on_iris33(struct msm_vidc_core *core) __interrupt_init_iris33(core); core->intr_status = 0; - enable_irq(core->dt->irq); + enable_irq(core->resource->irq); return rc; diff --git a/driver/variant/iris33/src/msm_vidc_power_iris33.c b/driver/variant/iris33/src/msm_vidc_power_iris33.c index c905d4cbce..1136cfb3f2 100644 --- a/driver/variant/iris33/src/msm_vidc_power_iris33.c +++ b/driver/variant/iris33/src/msm_vidc_power_iris33.c @@ -9,7 +9,6 @@ #include "msm_vidc_core.h" #include "msm_vidc_driver.h" #include "msm_vidc_debug.h" -#include "msm_vidc_dt.h" u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size) { @@ -27,9 +26,9 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size) d_vpr_e("%s: invalid params\n", __func__); return freq; } - core = inst->core; - if (!core->dt || !core->dt->allowed_clks_tbl) { + + if (!core->resource || !core->resource->freq_set.freq_tbl) { d_vpr_e("%s: invalid params\n", __func__); return freq; } @@ -151,8 +150,8 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size) u32 bitrate_2stage[2] = {130, 120}; u32 bitrate_1stage = 100; u32 width, height; - u32 bitrate_entry, freq_entry, frequency_table_value; - struct allowed_clock_rates_table *allowed_clks_tbl; + u32 bitrate_entry, freq_entry, freq_tbl_value; + struct frequency_table *freq_tbl; struct v4l2_format *out_f = &inst->fmts[OUTPUT_PORT]; width = out_f->fmt.pix_mp.width; @@ -165,11 +164,11 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size) freq_entry = bitrate_entry; - allowed_clks_tbl = core->dt->allowed_clks_tbl; - frequency_table_value = allowed_clks_tbl[freq_entry].clock_rate / 1000000; + freq_tbl = core->resource->freq_set.freq_tbl; + freq_tbl_value = freq_tbl[freq_entry].freq / 1000000; input_bitrate_mbps = fps * data_size * 8 / (1024 * 1024); - vsp_hw_min_frequency = frequency_table_value * 1000 * input_bitrate_mbps; + vsp_hw_min_frequency = freq_tbl_value * 1000 * input_bitrate_mbps; if (inst->capabilities->cap[STAGE].value == MSM_VIDC_STAGE_2) { vsp_hw_min_frequency += @@ -233,9 +232,9 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size) * for non-AV1 codecs limit the frequency to NOM only * index 0 is TURBO, index 1 is NOM clock rate */ - if (core->dt->allowed_clks_tbl_size >= 2 && - freq > core->dt->allowed_clks_tbl[1].clock_rate) - freq = core->dt->allowed_clks_tbl[1].clock_rate; + if (core->resource->freq_set.count >= 2 && + freq > core->resource->freq_set.freq_tbl[1].freq) + freq = core->resource->freq_set.freq_tbl[1].freq; } i_vpr_p(inst, "%s: filled len %d, required freq %llu, fps %u, mbpf %u\n", diff --git a/driver/vidc/inc/venus_hfi.h b/driver/vidc/inc/venus_hfi.h index 99058da742..650e8eb305 100644 --- a/driver/vidc/inc/venus_hfi.h +++ b/driver/vidc/inc/venus_hfi.h @@ -11,7 +11,6 @@ #include #include -#include "msm_vidc_dt.h" #include "msm_vidc_internal.h" #include "msm_vidc_inst.h" #include "msm_vidc_core.h" diff --git a/driver/vidc/src/msm_vdec.c b/driver/vidc/src/msm_vdec.c index 0bde551cbf..fbd3282dd9 100644 --- a/driver/vidc/src/msm_vdec.c +++ b/driver/vidc/src/msm_vdec.c @@ -12,7 +12,6 @@ #include "msm_vidc_inst.h" #include "msm_vidc_driver.h" #include "msm_vidc_internal.h" -#include "msm_vidc_platform.h" #include "msm_vidc_control.h" #include "msm_vidc_debug.h" #include "msm_vidc_power.h" diff --git a/driver/vidc/src/msm_venc.c b/driver/vidc/src/msm_venc.c index 19c393a913..28dc40eafd 100644 --- a/driver/vidc/src/msm_venc.c +++ b/driver/vidc/src/msm_venc.c @@ -10,7 +10,6 @@ #include "msm_vidc_inst.h" #include "msm_vidc_driver.h" #include "msm_vidc_internal.h" -#include "msm_vidc_platform.h" #include "msm_vidc_control.h" #include "msm_vidc_debug.h" #include "msm_vidc_power.h" diff --git a/driver/vidc/src/msm_vidc_control_ext.c b/driver/vidc/src/msm_vidc_control_ext.c index b526f2df19..ba127cc076 100644 --- a/driver/vidc/src/msm_vidc_control_ext.c +++ b/driver/vidc/src/msm_vidc_control_ext.c @@ -12,7 +12,6 @@ #include "msm_vidc_internal.h" #include "msm_vidc_driver.h" #include "msm_venc.h" -#include "msm_vidc_platform.h" int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl) {