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disp: msm: dsi: enable dfps trigger at mdp intf flush

Bladeren bron 
This change allows dynamic refresh trigger to sw trigger
and mdp intf flush. With this we can make sure that DSI
timing/clock update and mdp intf timings are updated in
one vsync.

Change-Id: Ic807f498e2e47be6dd0f1e11ff1fc0896a8ec758
Signed-off-by: Vara Reddy <varar@codeaurora.org>
This commit is contained in:
Vara Reddy
2020-08-18 08:45:42 -07:00
bovenliggende c75b0eb0a0
commit c9cb9f51f3
8 gewijzigde bestanden met toevoegingen van 117 en 2 verwijderingen
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19
msm/dsi/dsi_phy_hw_v4_0.c
Bestand weergeven

@@ -755,6 +755,23 @@ void dsi_phy_hw_v4_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy,
delay->pll_delay);
}
void dsi_phy_hw_v4_0_dyn_refresh_trigger_sel(struct dsi_phy_hw *phy,
bool is_master)
{
u32 reg;
/*
* Dynamic refresh will take effect at next mdp flush event.
* This makes sure that any update to frame timings together
* with dfps will take effect in one vsync at next mdp flush.
*/
if (is_master) {
reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
reg |= BIT(17);
DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
}
}
void dsi_phy_hw_v4_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset)
{
u32 reg;
@@ -766,7 +783,7 @@ void dsi_phy_hw_v4_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset)
*/
if (!offset) {
reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL);
reg &= ~(BIT(0) | BIT(8));
reg &= ~(BIT(0) | BIT(8) | BIT(13) | BIT(16) | BIT(17));
DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg);
wmb(); /* ensure dynamic fps is cleared */
return;