disp: msm: dsi: enable dfps trigger at mdp intf flush

This change allows dynamic refresh trigger to sw trigger
and mdp intf flush. With this we can make sure that DSI
timing/clock update and mdp intf timings are updated in
one vsync.

Change-Id: Ic807f498e2e47be6dd0f1e11ff1fc0896a8ec758
Signed-off-by: Vara Reddy <varar@codeaurora.org>
此提交包含在:
Vara Reddy
2020-08-18 08:45:42 -07:00
父節點 c75b0eb0a0
當前提交 c9cb9f51f3
共有 8 個檔案被更改,包括 117 行新增2 行删除

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@@ -201,6 +201,7 @@ static void dsi_catalog_phy_2_0_init(struct dsi_phy_hw *phy)
dsi_phy_hw_v2_0_dyn_refresh_pipe_delay;
phy->ops.dyn_refresh_ops.dyn_refresh_helper =
dsi_phy_hw_v2_0_dyn_refresh_helper;
phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel = NULL;
phy->ops.dyn_refresh_ops.cache_phy_timings =
dsi_phy_hw_v2_0_cache_phy_timings;
}
@@ -236,6 +237,7 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy)
dsi_phy_hw_v3_0_dyn_refresh_pipe_delay;
phy->ops.dyn_refresh_ops.dyn_refresh_helper =
dsi_phy_hw_v3_0_dyn_refresh_helper;
phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel = NULL;
phy->ops.dyn_refresh_ops.cache_phy_timings =
dsi_phy_hw_v3_0_cache_phy_timings;
}
@@ -272,6 +274,8 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
dsi_phy_hw_v4_0_dyn_refresh_pipe_delay;
phy->ops.dyn_refresh_ops.dyn_refresh_helper =
dsi_phy_hw_v4_0_dyn_refresh_helper;
phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel =
dsi_phy_hw_v4_0_dyn_refresh_trigger_sel;
phy->ops.dyn_refresh_ops.cache_phy_timings =
dsi_phy_hw_v4_0_cache_phy_timings;
phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk;