ASoC: wcd938x: Add support for wcd938x codec
WCD938x codec is a soundwire based codec that supports AMICs, DMICs, Headphones, Ear and Aux paths. Add support to enable all device paths of wcd938x codec. Change-Id: I81b5e603ef73afba74b8d2274012752f9ca5cb6f Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
This commit is contained in:
Sudheer Papothi
@@ -35,3 +35,10 @@ include $(MY_LOCAL_PATH)/asoc/codecs/bolero/Android.mk
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$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers)
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$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers)
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include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk
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include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk
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endif
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endif
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ifeq ($(call is-board-platform-in-list, kona),true)
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$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/bolero/Module.symvers)
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include $(MY_LOCAL_PATH)/asoc/codecs/bolero/Android.mk
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$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd938x/Module.symvers)
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include $(MY_LOCAL_PATH)/asoc/codecs/wcd938x/Android.mk
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endif
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57
asoc/codecs/wcd938x/Android.mk
Normal file
57
asoc/codecs/wcd938x/Android.mk
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@@ -0,0 +1,57 @@
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# Android makefile for audio kernel modules
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# Assume no targets will be supported
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# Check if this driver needs be built for current target
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ifeq ($(call is-board-platform,kona),true)
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AUDIO_SELECT := CONFIG_SND_SOC_KONA=m
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endif
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AUDIO_CHIPSET := audio
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# Build/Package only in case of supported target
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ifeq ($(call is-board-platform-in-list,kona),true)
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LOCAL_PATH := $(call my-dir)
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# This makefile is only for DLKM
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ifneq ($(findstring vendor,$(LOCAL_PATH)),)
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ifneq ($(findstring opensource,$(LOCAL_PATH)),)
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AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel
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endif # opensource
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DLKM_DIR := $(TOP)/device/qcom/common/dlkm
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# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
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###########################################################
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# This is set once per LOCAL_PATH, not per (kernel) module
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KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
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# We are actually building audio.ko here, as per the
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# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
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# This means we need to rename the module to <chipset>_audio.ko
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# after audio.ko is built.
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KBUILD_OPTIONS += MODNAME=wcd938x_dlkm
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KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
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KBUILD_OPTIONS += $(AUDIO_SELECT)
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###########################################################
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include $(CLEAR_VARS)
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LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd938x.ko
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LOCAL_MODULE_KBUILD_NAME := wcd938x_dlkm.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_DEBUG_ENABLE := true
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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###########################################################
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include $(CLEAR_VARS)
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LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd938x_slave.ko
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LOCAL_MODULE_KBUILD_NAME := wcd938x_slave_dlkm.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_DEBUG_ENABLE := true
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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###########################################################
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endif # DLKM check
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endif # supported target check
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112
asoc/codecs/wcd938x/Kbuild
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112
asoc/codecs/wcd938x/Kbuild
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@@ -0,0 +1,112 @@
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# We can build either as part of a standalone Kernel build or as
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# an external module. Determine which mechanism is being used
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ifeq ($(MODNAME),)
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KERNEL_BUILD := 1
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else
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KERNEL_BUILD := 0
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endif
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ifeq ($(KERNEL_BUILD), 1)
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# These are configurable via Kconfig for kernel-based builds
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# Need to explicitly configure for Android-based builds
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AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.19
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AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
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endif
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ifeq ($(KERNEL_BUILD), 0)
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ifeq ($(CONFIG_ARCH_KONA), y)
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include $(AUDIO_ROOT)/config/konaauto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
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endif
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endif
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# As per target team, build is done as follows:
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# Defconfig : build with default flags
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# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
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# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
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# Perf : Using appropriate msmXXXX-perf_defconfig
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#
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# Shipment builds (user variants) should not have any debug feature
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# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
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# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
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# there is no other way to identify defconfig builds, QTI internal
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# representation of perf builds (identified using the string 'perf'),
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# is used to identify if the build is a slub or defconfig one. This
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# way no critical debug feature will be enabled for perf and shipment
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# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
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# config.
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############ UAPI ############
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UAPI_DIR := uapi
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UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
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############ COMMON ############
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COMMON_DIR := include
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COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
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############ WCD938X ############
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# for WCD938X Codec
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ifdef CONFIG_SND_SOC_WCD938X
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WCD938X_OBJS += wcd938x.o
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WCD938X_OBJS += wcd938x-regmap.o
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WCD938X_OBJS += wcd938x-tables.o
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WCD938X_OBJS += wcd938x-mbhc.o
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endif
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ifdef CONFIG_SND_SOC_WCD938X_SLAVE
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WCD938X_SLAVE_OBJS += wcd938x-slave.o
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endif
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LINUX_INC += -Iinclude/linux
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INCS += $(COMMON_INC) \
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$(UAPI_INC)
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EXTRA_CFLAGS += $(INCS)
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CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
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-DANI_LITTLE_BIT_ENDIAN \
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-DDOT11F_LITTLE_ENDIAN_HOST \
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-DANI_COMPILER_TYPE_GCC \
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-DANI_OS_TYPE_ANDROID=6 \
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-DPTT_SOCK_SVC_ENABLE \
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-Wall\
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-Werror\
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-D__linux__
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KBUILD_CPPFLAGS += $(CDEFINES)
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# Currently, for versions of gcc which support it, the kernel Makefile
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# is disabling the maybe-uninitialized warning. Re-enable it for the
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# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
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# will override the kernel settings.
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ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
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EXTRA_CFLAGS += -Wmaybe-uninitialized
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endif
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#EXTRA_CFLAGS += -Wmissing-prototypes
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ifeq ($(call cc-option-yn, -Wheader-guard),y)
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EXTRA_CFLAGS += -Wheader-guard
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endif
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ifeq ($(KERNEL_BUILD), 0)
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
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endif
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# Module information used by KBuild framework
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obj-$(CONFIG_SND_SOC_WCD938X) += wcd938x_dlkm.o
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wcd938x_dlkm-y := $(WCD938X_OBJS)
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obj-$(CONFIG_SND_SOC_WCD938X_SLAVE) += wcd938x_slave_dlkm.o
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wcd938x_slave_dlkm-y := $(WCD938X_SLAVE_OBJS)
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# inject some build related information
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DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"
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182
asoc/codecs/wcd938x/internal.h
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182
asoc/codecs/wcd938x/internal.h
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@@ -0,0 +1,182 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _WCD938X_INTERNAL_H
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#define _WCD938X_INTERNAL_H
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#include <asoc/wcd-mbhc-v2.h>
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#include <asoc/wcd-irq.h>
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#include "wcd938x-mbhc.h"
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#define WCD938X_MAX_MICBIAS 4
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/* Convert from vout ctl to micbias voltage in mV */
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#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
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#define MAX_PORT 8
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#define MAX_CH_PER_PORT 8
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enum {
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TX_HDR12 = 0,
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TX_HDR34,
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TX_HDR_MAX,
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};
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extern struct regmap_config wcd938x_regmap_config;
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struct codec_port_info {
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u32 slave_port_type;
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u32 master_port_type;
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u32 ch_mask;
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u32 num_ch;
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u32 ch_rate;
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};
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struct wcd938x_priv {
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struct device *dev;
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int variant;
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struct snd_soc_component *component;
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struct device_node *rst_np;
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struct regmap *regmap;
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struct swr_device *rx_swr_dev;
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struct swr_device *tx_swr_dev;
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s32 micb_ref[WCD938X_MAX_MICBIAS];
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s32 pullup_ref[WCD938X_MAX_MICBIAS];
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struct fw_info *fw_data;
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struct device_node *wcd_rst_np;
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struct mutex micb_lock;
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s32 dmic_0_1_clk_cnt;
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s32 dmic_2_3_clk_cnt;
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s32 dmic_4_5_clk_cnt;
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s32 dmic_6_7_clk_cnt;
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int hdr_en[TX_HDR_MAX];
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/* class h specific info */
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struct wcd_clsh_cdc_info clsh_info;
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/* mbhc module */
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struct wcd938x_mbhc *mbhc;
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u32 hph_mode;
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bool comp1_enable;
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bool comp2_enable;
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struct irq_domain *virq;
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struct wcd_irq_info irq_info;
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u32 rx_clk_cnt;
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int num_irq_regs;
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/* to track the status */
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unsigned long status_mask;
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u8 num_tx_ports;
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u8 num_rx_ports;
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struct codec_port_info
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tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
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struct codec_port_info
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rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
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struct regulator_bulk_data *supplies;
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struct notifier_block nblock;
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/* wcd callback to bolero */
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void *handle;
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int (*update_wcd_event)(void *handle, u16 event, u32 data);
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int (*register_notifier)(void *handle,
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struct notifier_block *nblock,
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bool enable);
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u32 version;
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/* Entry for version info */
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struct snd_info_entry *entry;
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struct snd_info_entry *version_entry;
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};
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struct wcd938x_micbias_setting {
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u8 ldoh_v;
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u32 cfilt1_mv;
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u32 micb1_mv;
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u32 micb2_mv;
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u32 micb3_mv;
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u32 micb4_mv;
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u8 bias1_cfilt_sel;
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};
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struct wcd938x_pdata {
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struct device_node *rst_np;
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struct device_node *rx_slave;
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struct device_node *tx_slave;
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struct wcd938x_micbias_setting micbias;
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struct cdc_regulator *regulator;
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int num_supplies;
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};
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struct wcd_ctrl_platform_data {
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void *handle;
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int (*update_wcd_event)(void *handle, u16 event, u32 data);
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int (*register_notifier)(void *handle,
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struct notifier_block *nblock,
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bool enable);
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};
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enum {
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WCD_RX1,
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WCD_RX2,
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WCD_RX3
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};
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enum {
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BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
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BOLERO_WCD_EVT_PA_OFF_PRE_SSR,
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BOLERO_WCD_EVT_SSR_DOWN,
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BOLERO_WCD_EVT_SSR_UP,
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BOLERO_WCD_EVT_CLK_NOTIFY,
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};
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enum {
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WCD_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
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WCD_BOLERO_EVT_IMPED_TRUE, /* for imped true */
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WCD_BOLERO_EVT_IMPED_FALSE, /* for imped false */
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};
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enum {
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/* INTR_CTRL_INT_MASK_0 */
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WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
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WCD938X_IRQ_MBHC_BUTTON_PRESS_DET,
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WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
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WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
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WCD938X_IRQ_MBHC_SW_DET,
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WCD938X_IRQ_HPHR_OCP_INT,
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WCD938X_IRQ_HPHR_CNP_INT,
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WCD938X_IRQ_HPHL_OCP_INT,
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/* INTR_CTRL_INT_MASK_1 */
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WCD938X_IRQ_HPHL_CNP_INT,
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WCD938X_IRQ_EAR_CNP_INT,
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WCD938X_IRQ_EAR_SCD_INT,
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WCD938X_IRQ_AUX_CNP_INT,
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WCD938X_IRQ_AUX_SCD_INT,
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WCD938X_IRQ_HPHL_PDM_WD_INT,
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WCD938X_IRQ_HPHR_PDM_WD_INT,
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WCD938X_IRQ_AUX_PDM_WD_INT,
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||||||
|
/* INTR_CTRL_INT_MASK_2 */
|
||||||
|
WCD938X_IRQ_LDORT_SCD_INT,
|
||||||
|
WCD938X_IRQ_MBHC_MOISTURE_INT,
|
||||||
|
WCD938X_IRQ_HPHL_SURGE_DET_INT,
|
||||||
|
WCD938X_IRQ_HPHR_SURGE_DET_INT,
|
||||||
|
WCD938X_NUM_IRQS,
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct wcd938x_mbhc *wcd938x_soc_get_mbhc(
|
||||||
|
struct snd_soc_component *component);
|
||||||
|
extern int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
|
||||||
|
int volt, int micb_num);
|
||||||
|
extern int wcd938x_get_micb_vout_ctl_val(u32 micb_mv);
|
||||||
|
extern int wcd938x_micbias_control(struct snd_soc_component *component,
|
||||||
|
int micb_num, int req, bool is_dapm);
|
||||||
|
extern int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
|
||||||
|
struct snd_soc_component *component);
|
||||||
|
#endif /* _WCD938X_INTERNAL_H */
|
||||||
1082
asoc/codecs/wcd938x/wcd938x-mbhc.c
Normal file
1082
asoc/codecs/wcd938x/wcd938x-mbhc.c
Normal file
File diff suppressed because it is too large
Load Diff
63
asoc/codecs/wcd938x/wcd938x-mbhc.h
Normal file
63
asoc/codecs/wcd938x/wcd938x-mbhc.h
Normal file
@@ -0,0 +1,63 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
#ifndef __WCD938X_MBHC_H__
|
||||||
|
#define __WCD938X_MBHC_H__
|
||||||
|
#include <asoc/wcd-mbhc-v2.h>
|
||||||
|
|
||||||
|
struct wcd938x_mbhc {
|
||||||
|
struct wcd_mbhc wcd_mbhc;
|
||||||
|
struct blocking_notifier_head notifier;
|
||||||
|
struct fw_info *fw_data;
|
||||||
|
};
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_SND_SOC_WCD938X)
|
||||||
|
extern int wcd938x_mbhc_init(struct wcd938x_mbhc **mbhc,
|
||||||
|
struct snd_soc_component *component,
|
||||||
|
struct fw_info *fw_data);
|
||||||
|
extern void wcd938x_mbhc_hs_detect_exit(struct snd_soc_component *component);
|
||||||
|
extern int wcd938x_mbhc_hs_detect(struct snd_soc_component *component,
|
||||||
|
struct wcd_mbhc_config *mbhc_cfg);
|
||||||
|
extern void wcd938x_mbhc_deinit(struct snd_soc_component *component);
|
||||||
|
extern int wcd938x_mbhc_post_ssr_init(struct wcd938x_mbhc *mbhc,
|
||||||
|
struct snd_soc_component *component);
|
||||||
|
extern int wcd938x_mbhc_get_impedance(struct wcd938x_mbhc *wcd938x_mbhc,
|
||||||
|
uint32_t *zl, uint32_t *zr);
|
||||||
|
#else
|
||||||
|
static inline int wcd938x_mbhc_init(struct wcd938x_mbhc **mbhc,
|
||||||
|
struct snd_soc_component *component,
|
||||||
|
struct fw_info *fw_data)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
static inline void wcd938x_mbhc_hs_detect_exit(
|
||||||
|
struct snd_soc_component *component)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
static inline int wcd938x_mbhc_hs_detect(struct snd_soc_component *component,
|
||||||
|
struct wcd_mbhc_config *mbhc_cfg)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
static inline void wcd938x_mbhc_deinit(struct snd_soc_component *component)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
static inline int wcd938x_mbhc_post_ssr_init(struct wcd938x_mbhc *mbhc,
|
||||||
|
struct snd_soc_component *component)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int wcd938x_mbhc_get_impedance(struct wcd938x_mbhc *wcd938x_mbhc,
|
||||||
|
uint32_t *zl, uint32_t *zr)
|
||||||
|
{
|
||||||
|
if (zl)
|
||||||
|
*zl = 0;
|
||||||
|
if (zr)
|
||||||
|
*zr = 0;
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __WCD938X_MBHC_H__ */
|
||||||
502
asoc/codecs/wcd938x/wcd938x-registers.h
Normal file
502
asoc/codecs/wcd938x/wcd938x-registers.h
Normal file
@@ -0,0 +1,502 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _WCD938X_REGISTERS_H
|
||||||
|
#define _WCD938X_REGISTERS_H
|
||||||
|
|
||||||
|
#define WCD938X_BASE_ADDRESS 0x3000
|
||||||
|
#define WCD938X_REG(reg) (reg - WCD938X_BASE_ADDRESS)
|
||||||
|
|
||||||
|
enum {
|
||||||
|
REG_NO_ACCESS,
|
||||||
|
RD_REG,
|
||||||
|
WR_REG,
|
||||||
|
RD_WR_REG
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
#define WCD938X_ANA_PAGE_REGISTER (WCD938X_BASE_ADDRESS + 0x0000)
|
||||||
|
#define WCD938X_ANA_BIAS (WCD938X_BASE_ADDRESS + 0x0001)
|
||||||
|
#define WCD938X_ANA_RX_SUPPLIES (WCD938X_BASE_ADDRESS + 0x0008)
|
||||||
|
#define WCD938X_ANA_HPH (WCD938X_BASE_ADDRESS + 0x0009)
|
||||||
|
#define WCD938X_ANA_EAR (WCD938X_BASE_ADDRESS + 0x000A)
|
||||||
|
#define WCD938X_ANA_EAR_COMPANDER_CTL (WCD938X_BASE_ADDRESS + 0x000B)
|
||||||
|
#define WCD938X_ANA_TX_CH1 (WCD938X_BASE_ADDRESS + 0x000E)
|
||||||
|
#define WCD938X_ANA_TX_CH2 (WCD938X_BASE_ADDRESS + 0x000F)
|
||||||
|
#define WCD938X_ANA_TX_CH3 (WCD938X_BASE_ADDRESS + 0x0010)
|
||||||
|
#define WCD938X_ANA_TX_CH4 (WCD938X_BASE_ADDRESS + 0x0011)
|
||||||
|
#define WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC (WCD938X_BASE_ADDRESS + 0x0012)
|
||||||
|
#define WCD938X_ANA_MICB3_DSP_EN_LOGIC (WCD938X_BASE_ADDRESS + 0x0013)
|
||||||
|
#define WCD938X_ANA_MBHC_MECH (WCD938X_BASE_ADDRESS + 0x0014)
|
||||||
|
#define WCD938X_ANA_MBHC_ELECT (WCD938X_BASE_ADDRESS + 0x0015)
|
||||||
|
#define WCD938X_ANA_MBHC_ZDET (WCD938X_BASE_ADDRESS + 0x0016)
|
||||||
|
#define WCD938X_ANA_MBHC_RESULT_1 (WCD938X_BASE_ADDRESS + 0x0017)
|
||||||
|
#define WCD938X_ANA_MBHC_RESULT_2 (WCD938X_BASE_ADDRESS + 0x0018)
|
||||||
|
#define WCD938X_ANA_MBHC_RESULT_3 (WCD938X_BASE_ADDRESS + 0x0019)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN0 (WCD938X_BASE_ADDRESS + 0x001A)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN1 (WCD938X_BASE_ADDRESS + 0x001B)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN2 (WCD938X_BASE_ADDRESS + 0x001C)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN3 (WCD938X_BASE_ADDRESS + 0x001D)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN4 (WCD938X_BASE_ADDRESS + 0x001E)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN5 (WCD938X_BASE_ADDRESS + 0x001F)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN6 (WCD938X_BASE_ADDRESS + 0x0020)
|
||||||
|
#define WCD938X_ANA_MBHC_BTN7 (WCD938X_BASE_ADDRESS + 0x0021)
|
||||||
|
#define WCD938X_ANA_MICB1 (WCD938X_BASE_ADDRESS + 0x0022)
|
||||||
|
#define WCD938X_ANA_MICB2 (WCD938X_BASE_ADDRESS + 0x0023)
|
||||||
|
#define WCD938X_ANA_MICB2_RAMP (WCD938X_BASE_ADDRESS + 0x0024)
|
||||||
|
#define WCD938X_ANA_MICB3 (WCD938X_BASE_ADDRESS + 0x0025)
|
||||||
|
#define WCD938X_ANA_MICB4 (WCD938X_BASE_ADDRESS + 0x0026)
|
||||||
|
#define WCD938X_BIAS_CTL (WCD938X_BASE_ADDRESS + 0x0028)
|
||||||
|
#define WCD938X_BIAS_VBG_FINE_ADJ (WCD938X_BASE_ADDRESS + 0x0029)
|
||||||
|
#define WCD938X_LDOL_VDDCX_ADJUST (WCD938X_BASE_ADDRESS + 0x0040)
|
||||||
|
#define WCD938X_LDOL_DISABLE_LDOL (WCD938X_BASE_ADDRESS + 0x0041)
|
||||||
|
#define WCD938X_MBHC_CTL_CLK (WCD938X_BASE_ADDRESS + 0x0056)
|
||||||
|
#define WCD938X_MBHC_CTL_ANA (WCD938X_BASE_ADDRESS + 0x0057)
|
||||||
|
#define WCD938X_MBHC_CTL_SPARE_1 (WCD938X_BASE_ADDRESS + 0x0058)
|
||||||
|
#define WCD938X_MBHC_CTL_SPARE_2 (WCD938X_BASE_ADDRESS + 0x0059)
|
||||||
|
#define WCD938X_MBHC_CTL_BCS (WCD938X_BASE_ADDRESS + 0x005A)
|
||||||
|
#define WCD938X_MBHC_MOISTURE_DET_FSM_STATUS (WCD938X_BASE_ADDRESS + 0x005B)
|
||||||
|
#define WCD938X_MBHC_TEST_CTL (WCD938X_BASE_ADDRESS + 0x005C)
|
||||||
|
#define WCD938X_LDOH_MODE (WCD938X_BASE_ADDRESS + 0x0067)
|
||||||
|
#define WCD938X_LDOH_BIAS (WCD938X_BASE_ADDRESS + 0x0068)
|
||||||
|
#define WCD938X_LDOH_STB_LOADS (WCD938X_BASE_ADDRESS + 0x0069)
|
||||||
|
#define WCD938X_LDOH_SLOWRAMP (WCD938X_BASE_ADDRESS + 0x006A)
|
||||||
|
#define WCD938X_MICB1_TEST_CTL_1 (WCD938X_BASE_ADDRESS + 0x006B)
|
||||||
|
#define WCD938X_MICB1_TEST_CTL_2 (WCD938X_BASE_ADDRESS + 0x006C)
|
||||||
|
#define WCD938X_MICB1_TEST_CTL_3 (WCD938X_BASE_ADDRESS + 0x006D)
|
||||||
|
#define WCD938X_MICB2_TEST_CTL_1 (WCD938X_BASE_ADDRESS + 0x006E)
|
||||||
|
#define WCD938X_MICB2_TEST_CTL_2 (WCD938X_BASE_ADDRESS + 0x006F)
|
||||||
|
#define WCD938X_MICB2_TEST_CTL_3 (WCD938X_BASE_ADDRESS + 0x0070)
|
||||||
|
#define WCD938X_MICB3_TEST_CTL_1 (WCD938X_BASE_ADDRESS + 0x0071)
|
||||||
|
#define WCD938X_MICB3_TEST_CTL_2 (WCD938X_BASE_ADDRESS + 0x0072)
|
||||||
|
#define WCD938X_MICB3_TEST_CTL_3 (WCD938X_BASE_ADDRESS + 0x0073)
|
||||||
|
#define WCD938X_MICB4_TEST_CTL_1 (WCD938X_BASE_ADDRESS + 0x0074)
|
||||||
|
#define WCD938X_MICB4_TEST_CTL_2 (WCD938X_BASE_ADDRESS + 0x0075)
|
||||||
|
#define WCD938X_MICB4_TEST_CTL_3 (WCD938X_BASE_ADDRESS + 0x0076)
|
||||||
|
#define WCD938X_TX_COM_ADC_VCM (WCD938X_BASE_ADDRESS + 0x0077)
|
||||||
|
#define WCD938X_TX_COM_BIAS_ATEST (WCD938X_BASE_ADDRESS + 0x0078)
|
||||||
|
#define WCD938X_TX_COM_SPARE1 (WCD938X_BASE_ADDRESS + 0x0079)
|
||||||
|
#define WCD938X_TX_COM_SPARE2 (WCD938X_BASE_ADDRESS + 0x007A)
|
||||||
|
#define WCD938X_TX_COM_TXFE_DIV_CTL (WCD938X_BASE_ADDRESS + 0x007B)
|
||||||
|
#define WCD938X_TX_COM_TXFE_DIV_START (WCD938X_BASE_ADDRESS + 0x007C)
|
||||||
|
#define WCD938X_TX_COM_SPARE3 (WCD938X_BASE_ADDRESS + 0x007D)
|
||||||
|
#define WCD938X_TX_COM_SPARE4 (WCD938X_BASE_ADDRESS + 0x007E)
|
||||||
|
#define WCD938X_TX_1_2_TEST_EN (WCD938X_BASE_ADDRESS + 0x007F)
|
||||||
|
#define WCD938X_TX_1_2_ADC_IB (WCD938X_BASE_ADDRESS + 0x0080)
|
||||||
|
#define WCD938X_TX_1_2_ATEST_REFCTL (WCD938X_BASE_ADDRESS + 0x0081)
|
||||||
|
#define WCD938X_TX_1_2_TEST_CTL (WCD938X_BASE_ADDRESS + 0x0082)
|
||||||
|
#define WCD938X_TX_1_2_TEST_BLK_EN1 (WCD938X_BASE_ADDRESS + 0x0083)
|
||||||
|
#define WCD938X_TX_1_2_TXFE1_CLKDIV (WCD938X_BASE_ADDRESS + 0x0084)
|
||||||
|
#define WCD938X_TX_1_2_SAR2_ERR (WCD938X_BASE_ADDRESS + 0x0085)
|
||||||
|
#define WCD938X_TX_1_2_SAR1_ERR (WCD938X_BASE_ADDRESS + 0x0086)
|
||||||
|
#define WCD938X_TX_3_4_TEST_EN (WCD938X_BASE_ADDRESS + 0x0087)
|
||||||
|
#define WCD938X_TX_3_4_ADC_IB (WCD938X_BASE_ADDRESS + 0x0088)
|
||||||
|
#define WCD938X_TX_3_4_ATEST_REFCTL (WCD938X_BASE_ADDRESS + 0x0089)
|
||||||
|
#define WCD938X_TX_3_4_TEST_CTL (WCD938X_BASE_ADDRESS + 0x008A)
|
||||||
|
#define WCD938X_TX_3_4_TEST_BLK_EN3 (WCD938X_BASE_ADDRESS + 0x008B)
|
||||||
|
#define WCD938X_TX_3_4_TXFE3_CLKDIV (WCD938X_BASE_ADDRESS + 0x008C)
|
||||||
|
#define WCD938X_TX_3_4_SAR4_ERR (WCD938X_BASE_ADDRESS + 0x008D)
|
||||||
|
#define WCD938X_TX_3_4_SAR3_ERR (WCD938X_BASE_ADDRESS + 0x008E)
|
||||||
|
#define WCD938X_TX_3_4_TEST_BLK_EN2 (WCD938X_BASE_ADDRESS + 0x008F)
|
||||||
|
#define WCD938X_TX_3_4_TXFE2_CLKDIV (WCD938X_BASE_ADDRESS + 0x0090)
|
||||||
|
#define WCD938X_TX_3_4_SPARE1 (WCD938X_BASE_ADDRESS + 0x0091)
|
||||||
|
#define WCD938X_TX_3_4_TEST_BLK_EN4 (WCD938X_BASE_ADDRESS + 0x0092)
|
||||||
|
#define WCD938X_TX_3_4_TXFE4_CLKDIV (WCD938X_BASE_ADDRESS + 0x0093)
|
||||||
|
#define WCD938X_TX_3_4_SPARE2 (WCD938X_BASE_ADDRESS + 0x0094)
|
||||||
|
#define WCD938X_CLASSH_MODE_1 (WCD938X_BASE_ADDRESS + 0x0097)
|
||||||
|
#define WCD938X_CLASSH_MODE_2 (WCD938X_BASE_ADDRESS + 0x0098)
|
||||||
|
#define WCD938X_CLASSH_MODE_3 (WCD938X_BASE_ADDRESS + 0x0099)
|
||||||
|
#define WCD938X_CLASSH_CTRL_VCL_1 (WCD938X_BASE_ADDRESS + 0x009A)
|
||||||
|
#define WCD938X_CLASSH_CTRL_VCL_2 (WCD938X_BASE_ADDRESS + 0x009B)
|
||||||
|
#define WCD938X_CLASSH_CTRL_CCL_1 (WCD938X_BASE_ADDRESS + 0x009C)
|
||||||
|
#define WCD938X_CLASSH_CTRL_CCL_2 (WCD938X_BASE_ADDRESS + 0x009D)
|
||||||
|
#define WCD938X_CLASSH_CTRL_CCL_3 (WCD938X_BASE_ADDRESS + 0x009E)
|
||||||
|
#define WCD938X_CLASSH_CTRL_CCL_4 (WCD938X_BASE_ADDRESS + 0x009F)
|
||||||
|
#define WCD938X_CLASSH_CTRL_CCL_5 (WCD938X_BASE_ADDRESS + 0x00A0)
|
||||||
|
#define WCD938X_CLASSH_BUCK_TMUX_A_D (WCD938X_BASE_ADDRESS + 0x00A1)
|
||||||
|
#define WCD938X_CLASSH_BUCK_SW_DRV_CNTL (WCD938X_BASE_ADDRESS + 0x00A2)
|
||||||
|
#define WCD938X_CLASSH_SPARE (WCD938X_BASE_ADDRESS + 0x00A3)
|
||||||
|
#define WCD938X_FLYBACK_EN (WCD938X_BASE_ADDRESS + 0x00A4)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_1 (WCD938X_BASE_ADDRESS + 0x00A5)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_2 (WCD938X_BASE_ADDRESS + 0x00A6)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_3 (WCD938X_BASE_ADDRESS + 0x00A7)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_4 (WCD938X_BASE_ADDRESS + 0x00A8)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_5 (WCD938X_BASE_ADDRESS + 0x00A9)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_6 (WCD938X_BASE_ADDRESS + 0x00AA)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_7 (WCD938X_BASE_ADDRESS + 0x00AB)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_8 (WCD938X_BASE_ADDRESS + 0x00AC)
|
||||||
|
#define WCD938X_FLYBACK_VNEG_CTRL_9 (WCD938X_BASE_ADDRESS + 0x00AD)
|
||||||
|
#define WCD938X_FLYBACK_VNEGDAC_CTRL_1 (WCD938X_BASE_ADDRESS + 0x00AE)
|
||||||
|
#define WCD938X_FLYBACK_VNEGDAC_CTRL_2 (WCD938X_BASE_ADDRESS + 0x00AF)
|
||||||
|
#define WCD938X_FLYBACK_VNEGDAC_CTRL_3 (WCD938X_BASE_ADDRESS + 0x00B0)
|
||||||
|
#define WCD938X_FLYBACK_CTRL_1 (WCD938X_BASE_ADDRESS + 0x00B1)
|
||||||
|
#define WCD938X_FLYBACK_TEST_CTL (WCD938X_BASE_ADDRESS + 0x00B2)
|
||||||
|
#define WCD938X_RX_AUX_SW_CTL (WCD938X_BASE_ADDRESS + 0x00B3)
|
||||||
|
#define WCD938X_RX_PA_AUX_IN_CONN (WCD938X_BASE_ADDRESS + 0x00B4)
|
||||||
|
#define WCD938X_RX_TIMER_DIV (WCD938X_BASE_ADDRESS + 0x00B5)
|
||||||
|
#define WCD938X_RX_OCP_CTL (WCD938X_BASE_ADDRESS + 0x00B6)
|
||||||
|
#define WCD938X_RX_OCP_COUNT (WCD938X_BASE_ADDRESS + 0x00B7)
|
||||||
|
#define WCD938X_RX_BIAS_EAR_DAC (WCD938X_BASE_ADDRESS + 0x00B8)
|
||||||
|
#define WCD938X_RX_BIAS_EAR_AMP (WCD938X_BASE_ADDRESS + 0x00B9)
|
||||||
|
#define WCD938X_RX_BIAS_HPH_LDO (WCD938X_BASE_ADDRESS + 0x00BA)
|
||||||
|
#define WCD938X_RX_BIAS_HPH_PA (WCD938X_BASE_ADDRESS + 0x00BB)
|
||||||
|
#define WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2 (WCD938X_BASE_ADDRESS + 0x00BC)
|
||||||
|
#define WCD938X_RX_BIAS_HPH_RDAC_LDO (WCD938X_BASE_ADDRESS + 0x00BD)
|
||||||
|
#define WCD938X_RX_BIAS_HPH_CNP1 (WCD938X_BASE_ADDRESS + 0x00BE)
|
||||||
|
#define WCD938X_RX_BIAS_HPH_LOWPOWER (WCD938X_BASE_ADDRESS + 0x00BF)
|
||||||
|
#define WCD938X_RX_BIAS_AUX_DAC (WCD938X_BASE_ADDRESS + 0x00C0)
|
||||||
|
#define WCD938X_RX_BIAS_AUX_AMP (WCD938X_BASE_ADDRESS + 0x00C1)
|
||||||
|
#define WCD938X_RX_BIAS_VNEGDAC_BLEEDER (WCD938X_BASE_ADDRESS + 0x00C2)
|
||||||
|
#define WCD938X_RX_BIAS_MISC (WCD938X_BASE_ADDRESS + 0x00C3)
|
||||||
|
#define WCD938X_RX_BIAS_BUCK_RST (WCD938X_BASE_ADDRESS + 0x00C4)
|
||||||
|
#define WCD938X_RX_BIAS_BUCK_VREF_ERRAMP (WCD938X_BASE_ADDRESS + 0x00C5)
|
||||||
|
#define WCD938X_RX_BIAS_FLYB_ERRAMP (WCD938X_BASE_ADDRESS + 0x00C6)
|
||||||
|
#define WCD938X_RX_BIAS_FLYB_BUFF (WCD938X_BASE_ADDRESS + 0x00C7)
|
||||||
|
#define WCD938X_RX_BIAS_FLYB_MID_RST (WCD938X_BASE_ADDRESS + 0x00C8)
|
||||||
|
#define WCD938X_HPH_L_STATUS (WCD938X_BASE_ADDRESS + 0x00C9)
|
||||||
|
#define WCD938X_HPH_R_STATUS (WCD938X_BASE_ADDRESS + 0x00CA)
|
||||||
|
#define WCD938X_HPH_CNP_EN (WCD938X_BASE_ADDRESS + 0x00CB)
|
||||||
|
#define WCD938X_HPH_CNP_WG_CTL (WCD938X_BASE_ADDRESS + 0x00CC)
|
||||||
|
#define WCD938X_HPH_CNP_WG_TIME (WCD938X_BASE_ADDRESS + 0x00CD)
|
||||||
|
#define WCD938X_HPH_OCP_CTL (WCD938X_BASE_ADDRESS + 0x00CE)
|
||||||
|
#define WCD938X_HPH_AUTO_CHOP (WCD938X_BASE_ADDRESS + 0x00CF)
|
||||||
|
#define WCD938X_HPH_CHOP_CTL (WCD938X_BASE_ADDRESS + 0x00D0)
|
||||||
|
#define WCD938X_HPH_PA_CTL1 (WCD938X_BASE_ADDRESS + 0x00D1)
|
||||||
|
#define WCD938X_HPH_PA_CTL2 (WCD938X_BASE_ADDRESS + 0x00D2)
|
||||||
|
#define WCD938X_HPH_L_EN (WCD938X_BASE_ADDRESS + 0x00D3)
|
||||||
|
#define WCD938X_HPH_L_TEST (WCD938X_BASE_ADDRESS + 0x00D4)
|
||||||
|
#define WCD938X_HPH_L_ATEST (WCD938X_BASE_ADDRESS + 0x00D5)
|
||||||
|
#define WCD938X_HPH_R_EN (WCD938X_BASE_ADDRESS + 0x00D6)
|
||||||
|
#define WCD938X_HPH_R_TEST (WCD938X_BASE_ADDRESS + 0x00D7)
|
||||||
|
#define WCD938X_HPH_R_ATEST (WCD938X_BASE_ADDRESS + 0x00D8)
|
||||||
|
#define WCD938X_HPH_RDAC_CLK_CTL1 (WCD938X_BASE_ADDRESS + 0x00D9)
|
||||||
|
#define WCD938X_HPH_RDAC_CLK_CTL2 (WCD938X_BASE_ADDRESS + 0x00DA)
|
||||||
|
#define WCD938X_HPH_RDAC_LDO_CTL (WCD938X_BASE_ADDRESS + 0x00DB)
|
||||||
|
#define WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL (WCD938X_BASE_ADDRESS + 0x00DC)
|
||||||
|
#define WCD938X_HPH_REFBUFF_UHQA_CTL (WCD938X_BASE_ADDRESS + 0x00DD)
|
||||||
|
#define WCD938X_HPH_REFBUFF_LP_CTL (WCD938X_BASE_ADDRESS + 0x00DE)
|
||||||
|
#define WCD938X_HPH_L_DAC_CTL (WCD938X_BASE_ADDRESS + 0x00DF)
|
||||||
|
#define WCD938X_HPH_R_DAC_CTL (WCD938X_BASE_ADDRESS + 0x00E0)
|
||||||
|
#define WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD938X_BASE_ADDRESS + 0x00E1)
|
||||||
|
#define WCD938X_HPH_SURGE_HPHLR_SURGE_EN (WCD938X_BASE_ADDRESS + 0x00E2)
|
||||||
|
#define WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1 (WCD938X_BASE_ADDRESS + 0x00E3)
|
||||||
|
#define WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS (WCD938X_BASE_ADDRESS + 0x00E4)
|
||||||
|
#define WCD938X_EAR_EAR_EN_REG (WCD938X_BASE_ADDRESS + 0x00E9)
|
||||||
|
#define WCD938X_EAR_EAR_PA_CON (WCD938X_BASE_ADDRESS + 0x00EA)
|
||||||
|
#define WCD938X_EAR_EAR_SP_CON (WCD938X_BASE_ADDRESS + 0x00EB)
|
||||||
|
#define WCD938X_EAR_EAR_DAC_CON (WCD938X_BASE_ADDRESS + 0x00EC)
|
||||||
|
#define WCD938X_EAR_EAR_CNP_FSM_CON (WCD938X_BASE_ADDRESS + 0x00ED)
|
||||||
|
#define WCD938X_EAR_TEST_CTL (WCD938X_BASE_ADDRESS + 0x00EE)
|
||||||
|
#define WCD938X_EAR_STATUS_REG_1 (WCD938X_BASE_ADDRESS + 0x00EF)
|
||||||
|
#define WCD938X_EAR_STATUS_REG_2 (WCD938X_BASE_ADDRESS + 0x00F0)
|
||||||
|
#define WCD938X_ANA_NEW_PAGE_REGISTER (WCD938X_BASE_ADDRESS + 0x0100)
|
||||||
|
#define WCD938X_HPH_NEW_ANA_HPH2 (WCD938X_BASE_ADDRESS + 0x0101)
|
||||||
|
#define WCD938X_HPH_NEW_ANA_HPH3 (WCD938X_BASE_ADDRESS + 0x0102)
|
||||||
|
#define WCD938X_SLEEP_CTL (WCD938X_BASE_ADDRESS + 0x0103)
|
||||||
|
#define WCD938X_SLEEP_WATCHDOG_CTL (WCD938X_BASE_ADDRESS + 0x0104)
|
||||||
|
#define WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL (WCD938X_BASE_ADDRESS + 0x011F)
|
||||||
|
#define WCD938X_MBHC_NEW_CTL_1 (WCD938X_BASE_ADDRESS + 0x0120)
|
||||||
|
#define WCD938X_MBHC_NEW_CTL_2 (WCD938X_BASE_ADDRESS + 0x0121)
|
||||||
|
#define WCD938X_MBHC_NEW_PLUG_DETECT_CTL (WCD938X_BASE_ADDRESS + 0x0122)
|
||||||
|
#define WCD938X_MBHC_NEW_ZDET_ANA_CTL (WCD938X_BASE_ADDRESS + 0x0123)
|
||||||
|
#define WCD938X_MBHC_NEW_ZDET_RAMP_CTL (WCD938X_BASE_ADDRESS + 0x0124)
|
||||||
|
#define WCD938X_MBHC_NEW_FSM_STATUS (WCD938X_BASE_ADDRESS + 0x0125)
|
||||||
|
#define WCD938X_MBHC_NEW_ADC_RESULT (WCD938X_BASE_ADDRESS + 0x0126)
|
||||||
|
#define WCD938X_TX_NEW_AMIC_MUX_CFG (WCD938X_BASE_ADDRESS + 0x0127)
|
||||||
|
#define WCD938X_AUX_AUXPA (WCD938X_BASE_ADDRESS + 0x0128)
|
||||||
|
#define WCD938X_LDORXTX_MODE (WCD938X_BASE_ADDRESS + 0x0129)
|
||||||
|
#define WCD938X_LDORXTX_CONFIG (WCD938X_BASE_ADDRESS + 0x012A)
|
||||||
|
#define WCD938X_DIE_CRACK_DIE_CRK_DET_EN (WCD938X_BASE_ADDRESS + 0x012C)
|
||||||
|
#define WCD938X_DIE_CRACK_DIE_CRK_DET_OUT (WCD938X_BASE_ADDRESS + 0x012D)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL (WCD938X_BASE_ADDRESS + 0x0132)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L (WCD938X_BASE_ADDRESS + 0x0133)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_VREF_CTL (WCD938X_BASE_ADDRESS + 0x0134)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL (WCD938X_BASE_ADDRESS + 0x0135)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R (WCD938X_BASE_ADDRESS + 0x0136)
|
||||||
|
#define WCD938X_HPH_NEW_INT_PA_MISC1 (WCD938X_BASE_ADDRESS + 0x0137)
|
||||||
|
#define WCD938X_HPH_NEW_INT_PA_MISC2 (WCD938X_BASE_ADDRESS + 0x0138)
|
||||||
|
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC (WCD938X_BASE_ADDRESS + 0x0139)
|
||||||
|
#define WCD938X_HPH_NEW_INT_HPH_TIMER1 (WCD938X_BASE_ADDRESS + 0x013A)
|
||||||
|
#define WCD938X_HPH_NEW_INT_HPH_TIMER2 (WCD938X_BASE_ADDRESS + 0x013B)
|
||||||
|
#define WCD938X_HPH_NEW_INT_HPH_TIMER3 (WCD938X_BASE_ADDRESS + 0x013C)
|
||||||
|
#define WCD938X_HPH_NEW_INT_HPH_TIMER4 (WCD938X_BASE_ADDRESS + 0x013D)
|
||||||
|
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC2 (WCD938X_BASE_ADDRESS + 0x013E)
|
||||||
|
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC3 (WCD938X_BASE_ADDRESS + 0x013F)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW (WCD938X_BASE_ADDRESS + 0x0140)
|
||||||
|
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW (WCD938X_BASE_ADDRESS + 0x0141)
|
||||||
|
#define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD938X_BASE_ADDRESS + 0x0145)
|
||||||
|
#define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP (WCD938X_BASE_ADDRESS + 0x0146)
|
||||||
|
#define WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP (WCD938X_BASE_ADDRESS + 0x0147)
|
||||||
|
#define WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01AF)
|
||||||
|
#define WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01B0)
|
||||||
|
#define WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT (WCD938X_BASE_ADDRESS + 0x01B1)
|
||||||
|
#define WCD938X_MBHC_NEW_INT_SPARE_2 (WCD938X_BASE_ADDRESS + 0x01B2)
|
||||||
|
#define WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON (WCD938X_BASE_ADDRESS + 0x01B7)
|
||||||
|
#define WCD938X_EAR_INT_NEW_CNP_VCM_CON1 (WCD938X_BASE_ADDRESS + 0x01B8)
|
||||||
|
#define WCD938X_EAR_INT_NEW_CNP_VCM_CON2 (WCD938X_BASE_ADDRESS + 0x01B9)
|
||||||
|
#define WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS (WCD938X_BASE_ADDRESS + 0x01BA)
|
||||||
|
#define WCD938X_AUX_INT_EN_REG (WCD938X_BASE_ADDRESS + 0x01BD)
|
||||||
|
#define WCD938X_AUX_INT_PA_CTRL (WCD938X_BASE_ADDRESS + 0x01BE)
|
||||||
|
#define WCD938X_AUX_INT_SP_CTRL (WCD938X_BASE_ADDRESS + 0x01BF)
|
||||||
|
#define WCD938X_AUX_INT_DAC_CTRL (WCD938X_BASE_ADDRESS + 0x01C0)
|
||||||
|
#define WCD938X_AUX_INT_CLK_CTRL (WCD938X_BASE_ADDRESS + 0x01C1)
|
||||||
|
#define WCD938X_AUX_INT_TEST_CTRL (WCD938X_BASE_ADDRESS + 0x01C2)
|
||||||
|
#define WCD938X_AUX_INT_STATUS_REG (WCD938X_BASE_ADDRESS + 0x01C3)
|
||||||
|
#define WCD938X_AUX_INT_MISC (WCD938X_BASE_ADDRESS + 0x01C4)
|
||||||
|
#define WCD938X_LDORXTX_INT_BIAS (WCD938X_BASE_ADDRESS + 0x01C5)
|
||||||
|
#define WCD938X_LDORXTX_INT_STB_LOADS_DTEST (WCD938X_BASE_ADDRESS + 0x01C6)
|
||||||
|
#define WCD938X_LDORXTX_INT_TEST0 (WCD938X_BASE_ADDRESS + 0x01C7)
|
||||||
|
#define WCD938X_LDORXTX_INT_STARTUP_TIMER (WCD938X_BASE_ADDRESS + 0x01C8)
|
||||||
|
#define WCD938X_LDORXTX_INT_TEST1 (WCD938X_BASE_ADDRESS + 0x01C9)
|
||||||
|
#define WCD938X_LDORXTX_INT_STATUS (WCD938X_BASE_ADDRESS + 0x01CA)
|
||||||
|
#define WCD938X_SLEEP_INT_WATCHDOG_CTL_1 (WCD938X_BASE_ADDRESS + 0x01D0)
|
||||||
|
#define WCD938X_SLEEP_INT_WATCHDOG_CTL_2 (WCD938X_BASE_ADDRESS + 0x01D1)
|
||||||
|
#define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD938X_BASE_ADDRESS + 0x01D3)
|
||||||
|
#define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD938X_BASE_ADDRESS + 0x01D4)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 (WCD938X_BASE_ADDRESS + 0x01D5)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 (WCD938X_BASE_ADDRESS + 0x01D6)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 (WCD938X_BASE_ADDRESS + 0x01D7)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01D8)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01D9)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1 \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01DA)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0 \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01DB)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01DC)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1 \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01DD)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0 \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01DE)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01DF)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0 \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01E0)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01E1)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01E2)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP \
|
||||||
|
(WCD938X_BASE_ADDRESS + 0x01E3)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L2 (WCD938X_BASE_ADDRESS + 0x01E4)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L1 (WCD938X_BASE_ADDRESS + 0x01E5)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L0 (WCD938X_BASE_ADDRESS + 0x01E6)
|
||||||
|
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP (WCD938X_BASE_ADDRESS + 0x01E7)
|
||||||
|
#define WCD938X_DIGITAL_PAGE_REGISTER (WCD938X_BASE_ADDRESS + 0x0400)
|
||||||
|
#define WCD938X_DIGITAL_CHIP_ID0 (WCD938X_BASE_ADDRESS + 0x0401)
|
||||||
|
#define WCD938X_DIGITAL_CHIP_ID1 (WCD938X_BASE_ADDRESS + 0x0402)
|
||||||
|
#define WCD938X_DIGITAL_CHIP_ID2 (WCD938X_BASE_ADDRESS + 0x0403)
|
||||||
|
#define WCD938X_DIGITAL_CHIP_ID3 (WCD938X_BASE_ADDRESS + 0x0404)
|
||||||
|
#define WCD938X_DIGITAL_SWR_TX_CLK_RATE (WCD938X_BASE_ADDRESS + 0x0405)
|
||||||
|
#define WCD938X_DIGITAL_CDC_RST_CTL (WCD938X_BASE_ADDRESS + 0x0406)
|
||||||
|
#define WCD938X_DIGITAL_TOP_CLK_CFG (WCD938X_BASE_ADDRESS + 0x0407)
|
||||||
|
#define WCD938X_DIGITAL_CDC_ANA_CLK_CTL (WCD938X_BASE_ADDRESS + 0x0408)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DIG_CLK_CTL (WCD938X_BASE_ADDRESS + 0x0409)
|
||||||
|
#define WCD938X_DIGITAL_SWR_RST_EN (WCD938X_BASE_ADDRESS + 0x040A)
|
||||||
|
#define WCD938X_DIGITAL_CDC_PATH_MODE (WCD938X_BASE_ADDRESS + 0x040B)
|
||||||
|
#define WCD938X_DIGITAL_CDC_RX_RST (WCD938X_BASE_ADDRESS + 0x040C)
|
||||||
|
#define WCD938X_DIGITAL_CDC_RX0_CTL (WCD938X_BASE_ADDRESS + 0x040D)
|
||||||
|
#define WCD938X_DIGITAL_CDC_RX1_CTL (WCD938X_BASE_ADDRESS + 0x040E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_RX2_CTL (WCD938X_BASE_ADDRESS + 0x040F)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1 (WCD938X_BASE_ADDRESS + 0x0410)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3 (WCD938X_BASE_ADDRESS + 0x0411)
|
||||||
|
#define WCD938X_DIGITAL_CDC_COMP_CTL_0 (WCD938X_BASE_ADDRESS + 0x0414)
|
||||||
|
#define WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL (WCD938X_BASE_ADDRESS + 0x0417)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A1_0 (WCD938X_BASE_ADDRESS + 0x0418)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A1_1 (WCD938X_BASE_ADDRESS + 0x0419)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A2_0 (WCD938X_BASE_ADDRESS + 0x041A)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A2_1 (WCD938X_BASE_ADDRESS + 0x041B)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A3_0 (WCD938X_BASE_ADDRESS + 0x041C)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A3_1 (WCD938X_BASE_ADDRESS + 0x041D)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A4_0 (WCD938X_BASE_ADDRESS + 0x041E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A4_1 (WCD938X_BASE_ADDRESS + 0x041F)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A5_0 (WCD938X_BASE_ADDRESS + 0x0420)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A5_1 (WCD938X_BASE_ADDRESS + 0x0421)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A6_0 (WCD938X_BASE_ADDRESS + 0x0422)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_A7_0 (WCD938X_BASE_ADDRESS + 0x0423)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_0 (WCD938X_BASE_ADDRESS + 0x0424)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_1 (WCD938X_BASE_ADDRESS + 0x0425)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_2 (WCD938X_BASE_ADDRESS + 0x0426)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_3 (WCD938X_BASE_ADDRESS + 0x0427)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R1 (WCD938X_BASE_ADDRESS + 0x0428)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R2 (WCD938X_BASE_ADDRESS + 0x0429)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R3 (WCD938X_BASE_ADDRESS + 0x042A)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R4 (WCD938X_BASE_ADDRESS + 0x042B)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R5 (WCD938X_BASE_ADDRESS + 0x042C)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R6 (WCD938X_BASE_ADDRESS + 0x042D)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_DSM_R7 (WCD938X_BASE_ADDRESS + 0x042E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A1_0 (WCD938X_BASE_ADDRESS + 0x042F)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A1_1 (WCD938X_BASE_ADDRESS + 0x0430)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A2_0 (WCD938X_BASE_ADDRESS + 0x0431)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A2_1 (WCD938X_BASE_ADDRESS + 0x0432)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A3_0 (WCD938X_BASE_ADDRESS + 0x0433)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A3_1 (WCD938X_BASE_ADDRESS + 0x0434)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A4_0 (WCD938X_BASE_ADDRESS + 0x0435)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A4_1 (WCD938X_BASE_ADDRESS + 0x0436)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A5_0 (WCD938X_BASE_ADDRESS + 0x0437)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A5_1 (WCD938X_BASE_ADDRESS + 0x0438)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A6_0 (WCD938X_BASE_ADDRESS + 0x0439)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_A7_0 (WCD938X_BASE_ADDRESS + 0x043A)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_0 (WCD938X_BASE_ADDRESS + 0x043B)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_1 (WCD938X_BASE_ADDRESS + 0x043C)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_2 (WCD938X_BASE_ADDRESS + 0x043D)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_3 (WCD938X_BASE_ADDRESS + 0x043E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R1 (WCD938X_BASE_ADDRESS + 0x043F)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R2 (WCD938X_BASE_ADDRESS + 0x0440)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R3 (WCD938X_BASE_ADDRESS + 0x0441)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R4 (WCD938X_BASE_ADDRESS + 0x0442)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R5 (WCD938X_BASE_ADDRESS + 0x0443)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R6 (WCD938X_BASE_ADDRESS + 0x0444)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_DSM_R7 (WCD938X_BASE_ADDRESS + 0x0445)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0 (WCD938X_BASE_ADDRESS + 0x0446)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1 (WCD938X_BASE_ADDRESS + 0x0447)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0 (WCD938X_BASE_ADDRESS + 0x0448)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1 (WCD938X_BASE_ADDRESS + 0x0449)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2 (WCD938X_BASE_ADDRESS + 0x044A)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0 (WCD938X_BASE_ADDRESS + 0x044B)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1 (WCD938X_BASE_ADDRESS + 0x044C)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2 (WCD938X_BASE_ADDRESS + 0x044D)
|
||||||
|
#define WCD938X_DIGITAL_CDC_HPH_GAIN_CTL (WCD938X_BASE_ADDRESS + 0x044E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AUX_GAIN_CTL (WCD938X_BASE_ADDRESS + 0x044F)
|
||||||
|
#define WCD938X_DIGITAL_CDC_EAR_PATH_CTL (WCD938X_BASE_ADDRESS + 0x0450)
|
||||||
|
#define WCD938X_DIGITAL_CDC_SWR_CLH (WCD938X_BASE_ADDRESS + 0x0451)
|
||||||
|
#define WCD938X_DIGITAL_SWR_CLH_BYP (WCD938X_BASE_ADDRESS + 0x0452)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX0_CTL (WCD938X_BASE_ADDRESS + 0x0453)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX1_CTL (WCD938X_BASE_ADDRESS + 0x0454)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX2_CTL (WCD938X_BASE_ADDRESS + 0x0455)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX_RST (WCD938X_BASE_ADDRESS + 0x0456)
|
||||||
|
#define WCD938X_DIGITAL_CDC_REQ_CTL (WCD938X_BASE_ADDRESS + 0x0457)
|
||||||
|
#define WCD938X_DIGITAL_CDC_RST (WCD938X_BASE_ADDRESS + 0x0458)
|
||||||
|
#define WCD938X_DIGITAL_CDC_AMIC_CTL (WCD938X_BASE_ADDRESS + 0x045A)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC_CTL (WCD938X_BASE_ADDRESS + 0x045B)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC1_CTL (WCD938X_BASE_ADDRESS + 0x045C)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC2_CTL (WCD938X_BASE_ADDRESS + 0x045D)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC3_CTL (WCD938X_BASE_ADDRESS + 0x045E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC4_CTL (WCD938X_BASE_ADDRESS + 0x045F)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_PRG_CTL (WCD938X_BASE_ADDRESS + 0x0460)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_CTL (WCD938X_BASE_ADDRESS + 0x0461)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC_RATE_1_2 (WCD938X_BASE_ADDRESS + 0x0462)
|
||||||
|
#define WCD938X_DIGITAL_CDC_DMIC_RATE_3_4 (WCD938X_BASE_ADDRESS + 0x0463)
|
||||||
|
#define WCD938X_DIGITAL_PDM_WD_CTL0 (WCD938X_BASE_ADDRESS + 0x0465)
|
||||||
|
#define WCD938X_DIGITAL_PDM_WD_CTL1 (WCD938X_BASE_ADDRESS + 0x0466)
|
||||||
|
#define WCD938X_DIGITAL_PDM_WD_CTL2 (WCD938X_BASE_ADDRESS + 0x0467)
|
||||||
|
#define WCD938X_DIGITAL_INTR_MODE (WCD938X_BASE_ADDRESS + 0x046A)
|
||||||
|
#define WCD938X_DIGITAL_INTR_MASK_0 (WCD938X_BASE_ADDRESS + 0x046B)
|
||||||
|
#define WCD938X_DIGITAL_INTR_MASK_1 (WCD938X_BASE_ADDRESS + 0x046C)
|
||||||
|
#define WCD938X_DIGITAL_INTR_MASK_2 (WCD938X_BASE_ADDRESS + 0x046D)
|
||||||
|
#define WCD938X_DIGITAL_INTR_STATUS_0 (WCD938X_BASE_ADDRESS + 0x046E)
|
||||||
|
#define WCD938X_DIGITAL_INTR_STATUS_1 (WCD938X_BASE_ADDRESS + 0x046F)
|
||||||
|
#define WCD938X_DIGITAL_INTR_STATUS_2 (WCD938X_BASE_ADDRESS + 0x0470)
|
||||||
|
#define WCD938X_DIGITAL_INTR_CLEAR_0 (WCD938X_BASE_ADDRESS + 0x0471)
|
||||||
|
#define WCD938X_DIGITAL_INTR_CLEAR_1 (WCD938X_BASE_ADDRESS + 0x0472)
|
||||||
|
#define WCD938X_DIGITAL_INTR_CLEAR_2 (WCD938X_BASE_ADDRESS + 0x0473)
|
||||||
|
#define WCD938X_DIGITAL_INTR_LEVEL_0 (WCD938X_BASE_ADDRESS + 0x0474)
|
||||||
|
#define WCD938X_DIGITAL_INTR_LEVEL_1 (WCD938X_BASE_ADDRESS + 0x0475)
|
||||||
|
#define WCD938X_DIGITAL_INTR_LEVEL_2 (WCD938X_BASE_ADDRESS + 0x0476)
|
||||||
|
#define WCD938X_DIGITAL_INTR_SET_0 (WCD938X_BASE_ADDRESS + 0x0477)
|
||||||
|
#define WCD938X_DIGITAL_INTR_SET_1 (WCD938X_BASE_ADDRESS + 0x0478)
|
||||||
|
#define WCD938X_DIGITAL_INTR_SET_2 (WCD938X_BASE_ADDRESS + 0x0479)
|
||||||
|
#define WCD938X_DIGITAL_INTR_TEST_0 (WCD938X_BASE_ADDRESS + 0x047A)
|
||||||
|
#define WCD938X_DIGITAL_INTR_TEST_1 (WCD938X_BASE_ADDRESS + 0x047B)
|
||||||
|
#define WCD938X_DIGITAL_INTR_TEST_2 (WCD938X_BASE_ADDRESS + 0x047C)
|
||||||
|
#define WCD938X_DIGITAL_TX_MODE_DBG_EN (WCD938X_BASE_ADDRESS + 0x047F)
|
||||||
|
#define WCD938X_DIGITAL_TX_MODE_DBG_0_1 (WCD938X_BASE_ADDRESS + 0x0480)
|
||||||
|
#define WCD938X_DIGITAL_TX_MODE_DBG_2_3 (WCD938X_BASE_ADDRESS + 0x0481)
|
||||||
|
#define WCD938X_DIGITAL_LB_IN_SEL_CTL (WCD938X_BASE_ADDRESS + 0x0482)
|
||||||
|
#define WCD938X_DIGITAL_LOOP_BACK_MODE (WCD938X_BASE_ADDRESS + 0x0483)
|
||||||
|
#define WCD938X_DIGITAL_SWR_DAC_TEST (WCD938X_BASE_ADDRESS + 0x0484)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_RX_0 (WCD938X_BASE_ADDRESS + 0x0485)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_0 (WCD938X_BASE_ADDRESS + 0x0486)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_RX_1 (WCD938X_BASE_ADDRESS + 0x0487)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_1 (WCD938X_BASE_ADDRESS + 0x0488)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_2 (WCD938X_BASE_ADDRESS + 0x0489)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_0 (WCD938X_BASE_ADDRESS + 0x048A)
|
||||||
|
#define WCD938X_DIGITAL_SWR_HM_TEST_1 (WCD938X_BASE_ADDRESS + 0x048B)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_SWR_0 (WCD938X_BASE_ADDRESS + 0x048C)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_SWR_1 (WCD938X_BASE_ADDRESS + 0x048D)
|
||||||
|
#define WCD938X_DIGITAL_I2C_CTL (WCD938X_BASE_ADDRESS + 0x048E)
|
||||||
|
#define WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE (WCD938X_BASE_ADDRESS + 0x048F)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_TEST_CTL_0 (WCD938X_BASE_ADDRESS + 0x0490)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_TEST_CTL_1 (WCD938X_BASE_ADDRESS + 0x0491)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_T_DATA_0 (WCD938X_BASE_ADDRESS + 0x0492)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_T_DATA_1 (WCD938X_BASE_ADDRESS + 0x0493)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_PDM_RX0 (WCD938X_BASE_ADDRESS + 0x0494)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_PDM_RX1 (WCD938X_BASE_ADDRESS + 0x0495)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX0 (WCD938X_BASE_ADDRESS + 0x0496)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX1 (WCD938X_BASE_ADDRESS + 0x0497)
|
||||||
|
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX2 (WCD938X_BASE_ADDRESS + 0x0498)
|
||||||
|
#define WCD938X_DIGITAL_PAD_INP_DIS_0 (WCD938X_BASE_ADDRESS + 0x0499)
|
||||||
|
#define WCD938X_DIGITAL_PAD_INP_DIS_1 (WCD938X_BASE_ADDRESS + 0x049A)
|
||||||
|
#define WCD938X_DIGITAL_DRIVE_STRENGTH_0 (WCD938X_BASE_ADDRESS + 0x049B)
|
||||||
|
#define WCD938X_DIGITAL_DRIVE_STRENGTH_1 (WCD938X_BASE_ADDRESS + 0x049C)
|
||||||
|
#define WCD938X_DIGITAL_DRIVE_STRENGTH_2 (WCD938X_BASE_ADDRESS + 0x049D)
|
||||||
|
#define WCD938X_DIGITAL_RX_DATA_EDGE_CTL (WCD938X_BASE_ADDRESS + 0x049E)
|
||||||
|
#define WCD938X_DIGITAL_TX_DATA_EDGE_CTL (WCD938X_BASE_ADDRESS + 0x049F)
|
||||||
|
#define WCD938X_DIGITAL_GPIO_MODE (WCD938X_BASE_ADDRESS + 0x04A0)
|
||||||
|
#define WCD938X_DIGITAL_PIN_CTL_OE (WCD938X_BASE_ADDRESS + 0x04A1)
|
||||||
|
#define WCD938X_DIGITAL_PIN_CTL_DATA_0 (WCD938X_BASE_ADDRESS + 0x04A2)
|
||||||
|
#define WCD938X_DIGITAL_PIN_CTL_DATA_1 (WCD938X_BASE_ADDRESS + 0x04A3)
|
||||||
|
#define WCD938X_DIGITAL_PIN_STATUS_0 (WCD938X_BASE_ADDRESS + 0x04A4)
|
||||||
|
#define WCD938X_DIGITAL_PIN_STATUS_1 (WCD938X_BASE_ADDRESS + 0x04A5)
|
||||||
|
#define WCD938X_DIGITAL_DIG_DEBUG_CTL (WCD938X_BASE_ADDRESS + 0x04A6)
|
||||||
|
#define WCD938X_DIGITAL_DIG_DEBUG_EN (WCD938X_BASE_ADDRESS + 0x04A7)
|
||||||
|
#define WCD938X_DIGITAL_ANA_CSR_DBG_ADD (WCD938X_BASE_ADDRESS + 0x04A8)
|
||||||
|
#define WCD938X_DIGITAL_ANA_CSR_DBG_CTL (WCD938X_BASE_ADDRESS + 0x04A9)
|
||||||
|
#define WCD938X_DIGITAL_SSP_DBG (WCD938X_BASE_ADDRESS + 0x04AA)
|
||||||
|
#define WCD938X_DIGITAL_MODE_STATUS_0 (WCD938X_BASE_ADDRESS + 0x04AB)
|
||||||
|
#define WCD938X_DIGITAL_MODE_STATUS_1 (WCD938X_BASE_ADDRESS + 0x04AC)
|
||||||
|
#define WCD938X_DIGITAL_SPARE_0 (WCD938X_BASE_ADDRESS + 0x04AD)
|
||||||
|
#define WCD938X_DIGITAL_SPARE_1 (WCD938X_BASE_ADDRESS + 0x04AE)
|
||||||
|
#define WCD938X_DIGITAL_SPARE_2 (WCD938X_BASE_ADDRESS + 0x04AF)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_0 (WCD938X_BASE_ADDRESS + 0x04B0)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_1 (WCD938X_BASE_ADDRESS + 0x04B1)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_2 (WCD938X_BASE_ADDRESS + 0x04B2)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_3 (WCD938X_BASE_ADDRESS + 0x04B3)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_4 (WCD938X_BASE_ADDRESS + 0x04B4)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_5 (WCD938X_BASE_ADDRESS + 0x04B5)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_6 (WCD938X_BASE_ADDRESS + 0x04B6)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_7 (WCD938X_BASE_ADDRESS + 0x04B7)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_8 (WCD938X_BASE_ADDRESS + 0x04B8)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_9 (WCD938X_BASE_ADDRESS + 0x04B9)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_10 (WCD938X_BASE_ADDRESS + 0x04BA)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_11 (WCD938X_BASE_ADDRESS + 0x04BB)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_12 (WCD938X_BASE_ADDRESS + 0x04BC)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_13 (WCD938X_BASE_ADDRESS + 0x04BD)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_14 (WCD938X_BASE_ADDRESS + 0x04BE)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_15 (WCD938X_BASE_ADDRESS + 0x04BF)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_16 (WCD938X_BASE_ADDRESS + 0x04C0)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_17 (WCD938X_BASE_ADDRESS + 0x04C1)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_18 (WCD938X_BASE_ADDRESS + 0x04C2)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_19 (WCD938X_BASE_ADDRESS + 0x04C3)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_20 (WCD938X_BASE_ADDRESS + 0x04C4)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_21 (WCD938X_BASE_ADDRESS + 0x04C5)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_22 (WCD938X_BASE_ADDRESS + 0x04C6)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_23 (WCD938X_BASE_ADDRESS + 0x04C7)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_24 (WCD938X_BASE_ADDRESS + 0x04C8)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_25 (WCD938X_BASE_ADDRESS + 0x04C9)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_26 (WCD938X_BASE_ADDRESS + 0x04CA)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_27 (WCD938X_BASE_ADDRESS + 0x04CB)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_28 (WCD938X_BASE_ADDRESS + 0x04CC)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_29 (WCD938X_BASE_ADDRESS + 0x04CD)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_30 (WCD938X_BASE_ADDRESS + 0x04CE)
|
||||||
|
#define WCD938X_DIGITAL_EFUSE_REG_31 (WCD938X_BASE_ADDRESS + 0x04CF)
|
||||||
|
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_0 (WCD938X_BASE_ADDRESS + 0x04D0)
|
||||||
|
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_1 (WCD938X_BASE_ADDRESS + 0x04D1)
|
||||||
|
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_2 (WCD938X_BASE_ADDRESS + 0x04D2)
|
||||||
|
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_3 (WCD938X_BASE_ADDRESS + 0x04D3)
|
||||||
|
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_4 (WCD938X_BASE_ADDRESS + 0x04D4)
|
||||||
|
#define WCD938X_DIGITAL_DEM_BYPASS_DATA0 (WCD938X_BASE_ADDRESS + 0x04D5)
|
||||||
|
#define WCD938X_DIGITAL_DEM_BYPASS_DATA1 (WCD938X_BASE_ADDRESS + 0x04D6)
|
||||||
|
#define WCD938X_DIGITAL_DEM_BYPASS_DATA2 (WCD938X_BASE_ADDRESS + 0x04D7)
|
||||||
|
#define WCD938X_DIGITAL_DEM_BYPASS_DATA3 (WCD938X_BASE_ADDRESS + 0x04D8)
|
||||||
|
|
||||||
|
#define WCD938X_REGISTERS_MAX_SIZE (WCD938X_DIGITAL_DEM_BYPASS_DATA3 + 1)
|
||||||
|
#define WCD938X_MAX_REGISTER (WCD938X_REGISTERS_MAX_SIZE - 1)
|
||||||
|
|
||||||
|
#endif /*_WCD938X_REGISTERS_H*/
|
||||||
513
asoc/codecs/wcd938x/wcd938x-regmap.c
Normal file
513
asoc/codecs/wcd938x/wcd938x-regmap.c
Normal file
@@ -0,0 +1,513 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include "wcd938x-registers.h"
|
||||||
|
|
||||||
|
extern const u8 wcd938x_reg_access[WCD938X_REGISTERS_MAX_SIZE];
|
||||||
|
|
||||||
|
static const struct reg_default wcd938x_defaults[] = {
|
||||||
|
{WCD938X_ANA_PAGE_REGISTER, 0x00},
|
||||||
|
{WCD938X_ANA_BIAS, 0x00},
|
||||||
|
{WCD938X_ANA_RX_SUPPLIES, 0x00},
|
||||||
|
{WCD938X_ANA_HPH, 0x0C},
|
||||||
|
{WCD938X_ANA_EAR, 0x00},
|
||||||
|
{WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
|
||||||
|
{WCD938X_ANA_TX_CH1, 0x20},
|
||||||
|
{WCD938X_ANA_TX_CH2, 0x00},
|
||||||
|
{WCD938X_ANA_TX_CH3, 0x20},
|
||||||
|
{WCD938X_ANA_TX_CH4, 0x00},
|
||||||
|
{WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
|
||||||
|
{WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
|
||||||
|
{WCD938X_ANA_MBHC_MECH, 0x39},
|
||||||
|
{WCD938X_ANA_MBHC_ELECT, 0x08},
|
||||||
|
{WCD938X_ANA_MBHC_ZDET, 0x00},
|
||||||
|
{WCD938X_ANA_MBHC_RESULT_1, 0x00},
|
||||||
|
{WCD938X_ANA_MBHC_RESULT_2, 0x00},
|
||||||
|
{WCD938X_ANA_MBHC_RESULT_3, 0x00},
|
||||||
|
{WCD938X_ANA_MBHC_BTN0, 0x00},
|
||||||
|
{WCD938X_ANA_MBHC_BTN1, 0x10},
|
||||||
|
{WCD938X_ANA_MBHC_BTN2, 0x20},
|
||||||
|
{WCD938X_ANA_MBHC_BTN3, 0x30},
|
||||||
|
{WCD938X_ANA_MBHC_BTN4, 0x40},
|
||||||
|
{WCD938X_ANA_MBHC_BTN5, 0x50},
|
||||||
|
{WCD938X_ANA_MBHC_BTN6, 0x60},
|
||||||
|
{WCD938X_ANA_MBHC_BTN7, 0x70},
|
||||||
|
{WCD938X_ANA_MICB1, 0x10},
|
||||||
|
{WCD938X_ANA_MICB2, 0x10},
|
||||||
|
{WCD938X_ANA_MICB2_RAMP, 0x00},
|
||||||
|
{WCD938X_ANA_MICB3, 0x10},
|
||||||
|
{WCD938X_ANA_MICB4, 0x10},
|
||||||
|
{WCD938X_BIAS_CTL, 0x2A},
|
||||||
|
{WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
|
||||||
|
{WCD938X_LDOL_VDDCX_ADJUST, 0x01},
|
||||||
|
{WCD938X_LDOL_DISABLE_LDOL, 0x00},
|
||||||
|
{WCD938X_MBHC_CTL_CLK, 0x00},
|
||||||
|
{WCD938X_MBHC_CTL_ANA, 0x00},
|
||||||
|
{WCD938X_MBHC_CTL_SPARE_1, 0x00},
|
||||||
|
{WCD938X_MBHC_CTL_SPARE_2, 0x00},
|
||||||
|
{WCD938X_MBHC_CTL_BCS, 0x00},
|
||||||
|
{WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
|
||||||
|
{WCD938X_MBHC_TEST_CTL, 0x00},
|
||||||
|
{WCD938X_LDOH_MODE, 0x2B},
|
||||||
|
{WCD938X_LDOH_BIAS, 0x68},
|
||||||
|
{WCD938X_LDOH_STB_LOADS, 0x00},
|
||||||
|
{WCD938X_LDOH_SLOWRAMP, 0x50},
|
||||||
|
{WCD938X_MICB1_TEST_CTL_1, 0x1A},
|
||||||
|
{WCD938X_MICB1_TEST_CTL_2, 0x00},
|
||||||
|
{WCD938X_MICB1_TEST_CTL_3, 0xA4},
|
||||||
|
{WCD938X_MICB2_TEST_CTL_1, 0x1A},
|
||||||
|
{WCD938X_MICB2_TEST_CTL_2, 0x00},
|
||||||
|
{WCD938X_MICB2_TEST_CTL_3, 0x24},
|
||||||
|
{WCD938X_MICB3_TEST_CTL_1, 0x1A},
|
||||||
|
{WCD938X_MICB3_TEST_CTL_2, 0x00},
|
||||||
|
{WCD938X_MICB3_TEST_CTL_3, 0xA4},
|
||||||
|
{WCD938X_MICB4_TEST_CTL_1, 0x1A},
|
||||||
|
{WCD938X_MICB4_TEST_CTL_2, 0x00},
|
||||||
|
{WCD938X_MICB4_TEST_CTL_3, 0xA4},
|
||||||
|
{WCD938X_TX_COM_ADC_VCM, 0x39},
|
||||||
|
{WCD938X_TX_COM_BIAS_ATEST, 0xE0},
|
||||||
|
{WCD938X_TX_COM_SPARE1, 0x00},
|
||||||
|
{WCD938X_TX_COM_SPARE2, 0x00},
|
||||||
|
{WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
|
||||||
|
{WCD938X_TX_COM_TXFE_DIV_START, 0x00},
|
||||||
|
{WCD938X_TX_COM_SPARE3, 0x00},
|
||||||
|
{WCD938X_TX_COM_SPARE4, 0x00},
|
||||||
|
{WCD938X_TX_1_2_TEST_EN, 0xCC},
|
||||||
|
{WCD938X_TX_1_2_ADC_IB, 0xE9},
|
||||||
|
{WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
|
||||||
|
{WCD938X_TX_1_2_TEST_CTL, 0x38},
|
||||||
|
{WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
|
||||||
|
{WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
|
||||||
|
{WCD938X_TX_1_2_SAR2_ERR, 0x00},
|
||||||
|
{WCD938X_TX_1_2_SAR1_ERR, 0x00},
|
||||||
|
{WCD938X_TX_3_4_TEST_EN, 0xCC},
|
||||||
|
{WCD938X_TX_3_4_ADC_IB, 0xE9},
|
||||||
|
{WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
|
||||||
|
{WCD938X_TX_3_4_TEST_CTL, 0x38},
|
||||||
|
{WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
|
||||||
|
{WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
|
||||||
|
{WCD938X_TX_3_4_SAR4_ERR, 0x00},
|
||||||
|
{WCD938X_TX_3_4_SAR3_ERR, 0x00},
|
||||||
|
{WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
|
||||||
|
{WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
|
||||||
|
{WCD938X_TX_3_4_SPARE1, 0x00},
|
||||||
|
{WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
|
||||||
|
{WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
|
||||||
|
{WCD938X_TX_3_4_SPARE2, 0x00},
|
||||||
|
{WCD938X_CLASSH_MODE_1, 0x40},
|
||||||
|
{WCD938X_CLASSH_MODE_2, 0x3A},
|
||||||
|
{WCD938X_CLASSH_MODE_3, 0x00},
|
||||||
|
{WCD938X_CLASSH_CTRL_VCL_1, 0x70},
|
||||||
|
{WCD938X_CLASSH_CTRL_VCL_2, 0x82},
|
||||||
|
{WCD938X_CLASSH_CTRL_CCL_1, 0x31},
|
||||||
|
{WCD938X_CLASSH_CTRL_CCL_2, 0x80},
|
||||||
|
{WCD938X_CLASSH_CTRL_CCL_3, 0x80},
|
||||||
|
{WCD938X_CLASSH_CTRL_CCL_4, 0x51},
|
||||||
|
{WCD938X_CLASSH_CTRL_CCL_5, 0x00},
|
||||||
|
{WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
|
||||||
|
{WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
|
||||||
|
{WCD938X_CLASSH_SPARE, 0x00},
|
||||||
|
{WCD938X_FLYBACK_EN, 0x4E},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
|
||||||
|
{WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
|
||||||
|
{WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
|
||||||
|
{WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
|
||||||
|
{WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
|
||||||
|
{WCD938X_FLYBACK_CTRL_1, 0x65},
|
||||||
|
{WCD938X_FLYBACK_TEST_CTL, 0x00},
|
||||||
|
{WCD938X_RX_AUX_SW_CTL, 0x00},
|
||||||
|
{WCD938X_RX_PA_AUX_IN_CONN, 0x01},
|
||||||
|
{WCD938X_RX_TIMER_DIV, 0x32},
|
||||||
|
{WCD938X_RX_OCP_CTL, 0x1F},
|
||||||
|
{WCD938X_RX_OCP_COUNT, 0x77},
|
||||||
|
{WCD938X_RX_BIAS_EAR_DAC, 0xA0},
|
||||||
|
{WCD938X_RX_BIAS_EAR_AMP, 0xAA},
|
||||||
|
{WCD938X_RX_BIAS_HPH_LDO, 0xA9},
|
||||||
|
{WCD938X_RX_BIAS_HPH_PA, 0xAA},
|
||||||
|
{WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
|
||||||
|
{WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
|
||||||
|
{WCD938X_RX_BIAS_HPH_CNP1, 0x82},
|
||||||
|
{WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
|
||||||
|
{WCD938X_RX_BIAS_AUX_DAC, 0xA0},
|
||||||
|
{WCD938X_RX_BIAS_AUX_AMP, 0xAA},
|
||||||
|
{WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
|
||||||
|
{WCD938X_RX_BIAS_MISC, 0x00},
|
||||||
|
{WCD938X_RX_BIAS_BUCK_RST, 0x08},
|
||||||
|
{WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
|
||||||
|
{WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
|
||||||
|
{WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
|
||||||
|
{WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
|
||||||
|
{WCD938X_HPH_L_STATUS, 0x04},
|
||||||
|
{WCD938X_HPH_R_STATUS, 0x04},
|
||||||
|
{WCD938X_HPH_CNP_EN, 0x80},
|
||||||
|
{WCD938X_HPH_CNP_WG_CTL, 0x9A},
|
||||||
|
{WCD938X_HPH_CNP_WG_TIME, 0x14},
|
||||||
|
{WCD938X_HPH_OCP_CTL, 0x28},
|
||||||
|
{WCD938X_HPH_AUTO_CHOP, 0x16},
|
||||||
|
{WCD938X_HPH_CHOP_CTL, 0x83},
|
||||||
|
{WCD938X_HPH_PA_CTL1, 0x46},
|
||||||
|
{WCD938X_HPH_PA_CTL2, 0x50},
|
||||||
|
{WCD938X_HPH_L_EN, 0x80},
|
||||||
|
{WCD938X_HPH_L_TEST, 0xE0},
|
||||||
|
{WCD938X_HPH_L_ATEST, 0x50},
|
||||||
|
{WCD938X_HPH_R_EN, 0x80},
|
||||||
|
{WCD938X_HPH_R_TEST, 0xE0},
|
||||||
|
{WCD938X_HPH_R_ATEST, 0x54},
|
||||||
|
{WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
|
||||||
|
{WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
|
||||||
|
{WCD938X_HPH_RDAC_LDO_CTL, 0x33},
|
||||||
|
{WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
|
||||||
|
{WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
|
||||||
|
{WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
|
||||||
|
{WCD938X_HPH_L_DAC_CTL, 0x20},
|
||||||
|
{WCD938X_HPH_R_DAC_CTL, 0x20},
|
||||||
|
{WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
|
||||||
|
{WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
|
||||||
|
{WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
|
||||||
|
{WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
|
||||||
|
{WCD938X_EAR_EAR_EN_REG, 0x22},
|
||||||
|
{WCD938X_EAR_EAR_PA_CON, 0x44},
|
||||||
|
{WCD938X_EAR_EAR_SP_CON, 0xDB},
|
||||||
|
{WCD938X_EAR_EAR_DAC_CON, 0x80},
|
||||||
|
{WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
|
||||||
|
{WCD938X_EAR_TEST_CTL, 0x00},
|
||||||
|
{WCD938X_EAR_STATUS_REG_1, 0x00},
|
||||||
|
{WCD938X_EAR_STATUS_REG_2, 0x08},
|
||||||
|
{WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_ANA_HPH2, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_ANA_HPH3, 0x00},
|
||||||
|
{WCD938X_SLEEP_CTL, 0x16},
|
||||||
|
{WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
|
||||||
|
{WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
|
||||||
|
{WCD938X_MBHC_NEW_CTL_1, 0x02},
|
||||||
|
{WCD938X_MBHC_NEW_CTL_2, 0x05},
|
||||||
|
{WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
|
||||||
|
{WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
|
||||||
|
{WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
|
||||||
|
{WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
|
||||||
|
{WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
|
||||||
|
{WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
|
||||||
|
{WCD938X_AUX_AUXPA, 0x00},
|
||||||
|
{WCD938X_LDORXTX_MODE, 0x0C},
|
||||||
|
{WCD938X_LDORXTX_CONFIG, 0x10},
|
||||||
|
{WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
|
||||||
|
{WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
|
||||||
|
{WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
|
||||||
|
{WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
|
||||||
|
{WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
|
||||||
|
{WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
|
||||||
|
{WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
|
||||||
|
{WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
|
||||||
|
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
|
||||||
|
{WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
|
||||||
|
{WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
|
||||||
|
{WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
|
||||||
|
{WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
|
||||||
|
{WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
|
||||||
|
{WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
|
||||||
|
{WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
|
||||||
|
{WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
|
||||||
|
{WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
|
||||||
|
{WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
|
||||||
|
{WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
|
||||||
|
{WCD938X_AUX_INT_EN_REG, 0x00},
|
||||||
|
{WCD938X_AUX_INT_PA_CTRL, 0x06},
|
||||||
|
{WCD938X_AUX_INT_SP_CTRL, 0xD2},
|
||||||
|
{WCD938X_AUX_INT_DAC_CTRL, 0x80},
|
||||||
|
{WCD938X_AUX_INT_CLK_CTRL, 0x50},
|
||||||
|
{WCD938X_AUX_INT_TEST_CTRL, 0x00},
|
||||||
|
{WCD938X_AUX_INT_STATUS_REG, 0x00},
|
||||||
|
{WCD938X_AUX_INT_MISC, 0x00},
|
||||||
|
{WCD938X_LDORXTX_INT_BIAS, 0x6E},
|
||||||
|
{WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
|
||||||
|
{WCD938X_LDORXTX_INT_TEST0, 0x1C},
|
||||||
|
{WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
|
||||||
|
{WCD938X_LDORXTX_INT_TEST1, 0x1F},
|
||||||
|
{WCD938X_LDORXTX_INT_STATUS, 0x00},
|
||||||
|
{WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
|
||||||
|
{WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
|
||||||
|
{WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
|
||||||
|
{WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
|
||||||
|
{WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
|
||||||
|
{WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CHIP_ID0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CHIP_ID1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CHIP_ID2, 0x0D},
|
||||||
|
{WCD938X_DIGITAL_CHIP_ID3, 0x01},
|
||||||
|
{WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
|
||||||
|
{WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
|
||||||
|
{WCD938X_DIGITAL_SWR_RST_EN, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
|
||||||
|
{WCD938X_DIGITAL_CDC_RX_RST, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
|
||||||
|
{WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
|
||||||
|
{WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX_RST, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_RST, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
|
||||||
|
{WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
|
||||||
|
{WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_MODE, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
|
||||||
|
{WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_SET_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_SET_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_SET_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_TEST_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_TEST_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_INTR_TEST_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
|
||||||
|
{WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
|
||||||
|
{WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
|
||||||
|
{WCD938X_DIGITAL_I2C_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
|
||||||
|
{WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
|
||||||
|
{WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
|
||||||
|
{WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
|
||||||
|
{WCD938X_DIGITAL_GPIO_MODE, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
|
||||||
|
{WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
|
||||||
|
{WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
|
||||||
|
{WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
|
||||||
|
{WCD938X_DIGITAL_SSP_DBG, 0x00},
|
||||||
|
{WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SPARE_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SPARE_1, 0x00},
|
||||||
|
{WCD938X_DIGITAL_SPARE_2, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
|
||||||
|
{WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
|
||||||
|
{WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
|
||||||
|
{WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
|
||||||
|
{WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
|
||||||
|
{WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
|
||||||
|
{WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
|
||||||
|
{WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
|
||||||
|
{WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
|
||||||
|
{WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
|
||||||
|
{WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
|
||||||
|
};
|
||||||
|
|
||||||
|
static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
|
||||||
|
{
|
||||||
|
if(reg <= WCD938X_BASE_ADDRESS)
|
||||||
|
return 0;
|
||||||
|
return wcd938x_reg_access[WCD938X_REG(reg)] & RD_REG;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
|
||||||
|
{
|
||||||
|
if(reg <= WCD938X_BASE_ADDRESS)
|
||||||
|
return 0;
|
||||||
|
return wcd938x_reg_access[WCD938X_REG(reg)] & WR_REG;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
|
||||||
|
{
|
||||||
|
if(reg <= WCD938X_BASE_ADDRESS)
|
||||||
|
return 0;
|
||||||
|
return (wcd938x_reg_access[WCD938X_REG(reg)] & RD_REG)
|
||||||
|
& ~(wcd938x_reg_access[WCD938X_REG(reg)] & WR_REG);
|
||||||
|
}
|
||||||
|
|
||||||
|
struct regmap_config wcd938x_regmap_config = {
|
||||||
|
.name = "wcd938x_csr",
|
||||||
|
.reg_bits = 16,
|
||||||
|
.val_bits = 8,
|
||||||
|
.cache_type = REGCACHE_RBTREE,
|
||||||
|
.reg_defaults = wcd938x_defaults,
|
||||||
|
.num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
|
||||||
|
.max_register = WCD938X_MAX_REGISTER,
|
||||||
|
.readable_reg = wcd938x_readable_register,
|
||||||
|
.writeable_reg = wcd938x_writeable_register,
|
||||||
|
.volatile_reg = wcd938x_volatile_register,
|
||||||
|
.can_multi_write = true,
|
||||||
|
};
|
||||||
117
asoc/codecs/wcd938x/wcd938x-slave.c
Normal file
117
asoc/codecs/wcd938x/wcd938x-slave.c
Normal file
@@ -0,0 +1,117 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/component.h>
|
||||||
|
#include <soc/soundwire.h>
|
||||||
|
|
||||||
|
struct wcd938x_slave_priv {
|
||||||
|
struct swr_device *swr_slave;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int wcd938x_slave_bind(struct device *dev,
|
||||||
|
struct device *master, void *data)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
uint8_t devnum = 0;
|
||||||
|
struct swr_device *pdev = to_swr_device(dev);
|
||||||
|
|
||||||
|
ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
|
||||||
|
if (ret) {
|
||||||
|
dev_dbg(&pdev->dev,
|
||||||
|
"%s get devnum %d for dev addr %lx failed\n",
|
||||||
|
__func__, devnum, pdev->addr);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
pdev->dev_num = devnum;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void wcd938x_slave_unbind(struct device *dev,
|
||||||
|
struct device *master, void *data)
|
||||||
|
{
|
||||||
|
struct wcd938x_slave_priv *wcd938x_slave = NULL;
|
||||||
|
struct swr_device *pdev = to_swr_device(dev);
|
||||||
|
|
||||||
|
wcd938x_slave = swr_get_dev_data(pdev);
|
||||||
|
if (!wcd938x_slave) {
|
||||||
|
dev_err(&pdev->dev, "%s: wcd938x_slave is NULL\n", __func__);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct swr_device_id wcd938x_swr_id[] = {
|
||||||
|
{"wcd938x-slave", 0},
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct of_device_id wcd938x_swr_dt_match[] = {
|
||||||
|
{
|
||||||
|
.compatible = "qcom,wcd938x-slave",
|
||||||
|
},
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct component_ops wcd938x_slave_comp_ops = {
|
||||||
|
.bind = wcd938x_slave_bind,
|
||||||
|
.unbind = wcd938x_slave_unbind,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int wcd938x_swr_probe(struct swr_device *pdev)
|
||||||
|
{
|
||||||
|
struct wcd938x_slave_priv *wcd938x_slave = NULL;
|
||||||
|
|
||||||
|
wcd938x_slave = devm_kzalloc(&pdev->dev,
|
||||||
|
sizeof(struct wcd938x_slave_priv), GFP_KERNEL);
|
||||||
|
if (!wcd938x_slave)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
swr_set_dev_data(pdev, wcd938x_slave);
|
||||||
|
|
||||||
|
wcd938x_slave->swr_slave = pdev;
|
||||||
|
|
||||||
|
return component_add(&pdev->dev, &wcd938x_slave_comp_ops);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int wcd938x_swr_remove(struct swr_device *pdev)
|
||||||
|
{
|
||||||
|
component_del(&pdev->dev, &wcd938x_slave_comp_ops);
|
||||||
|
swr_set_dev_data(pdev, NULL);
|
||||||
|
swr_remove_device(pdev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct swr_driver wcd938x_slave_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "wcd938x-slave",
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.of_match_table = wcd938x_swr_dt_match,
|
||||||
|
},
|
||||||
|
.probe = wcd938x_swr_probe,
|
||||||
|
.remove = wcd938x_swr_remove,
|
||||||
|
.id_table = wcd938x_swr_id,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init wcd938x_slave_init(void)
|
||||||
|
{
|
||||||
|
return swr_driver_register(&wcd938x_slave_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit wcd938x_slave_exit(void)
|
||||||
|
{
|
||||||
|
swr_driver_unregister(&wcd938x_slave_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
module_init(wcd938x_slave_init);
|
||||||
|
module_exit(wcd938x_slave_exit);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("WCD938X Swr Slave driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
474
asoc/codecs/wcd938x/wcd938x-tables.c
Normal file
474
asoc/codecs/wcd938x/wcd938x-tables.c
Normal file
@@ -0,0 +1,474 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018 , The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include "wcd938x-registers.h"
|
||||||
|
|
||||||
|
const u8 wcd938x_reg_access[WCD938X_REG(WCD938X_REGISTERS_MAX_SIZE)] = {
|
||||||
|
[WCD938X_REG(WCD938X_ANA_PAGE_REGISTER)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_BIAS)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_RX_SUPPLIES)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_HPH)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_EAR)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_EAR_COMPANDER_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_TX_CH1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_TX_CH2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_TX_CH3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_TX_CH4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB3_DSP_EN_LOGIC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_MECH)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_ELECT)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_ZDET)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_RESULT_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_RESULT_2)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_RESULT_3)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN5)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN6)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MBHC_BTN7)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB2_RAMP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_MICB4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_BIAS_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_BIAS_VBG_FINE_ADJ)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDOL_VDDCX_ADJUST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDOL_DISABLE_LDOL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_CTL_CLK)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_CTL_ANA)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_CTL_SPARE_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_CTL_SPARE_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_CTL_BCS)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_MOISTURE_DET_FSM_STATUS)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_TEST_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDOH_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDOH_BIAS)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDOH_STB_LOADS)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDOH_SLOWRAMP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB1_TEST_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB1_TEST_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB1_TEST_CTL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB2_TEST_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB2_TEST_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB2_TEST_CTL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB3_TEST_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB3_TEST_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB3_TEST_CTL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB4_TEST_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB4_TEST_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MICB4_TEST_CTL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_ADC_VCM)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_BIAS_ATEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_SPARE1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_SPARE2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_TXFE_DIV_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_TXFE_DIV_START)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_SPARE3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_SPARE4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_TEST_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_ADC_IB)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_ATEST_REFCTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_TEST_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_TEST_BLK_EN1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_TXFE1_CLKDIV)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_SAR2_ERR)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_1_2_SAR1_ERR)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TEST_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_ADC_IB)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_ATEST_REFCTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TEST_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TEST_BLK_EN3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TXFE3_CLKDIV)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_SAR4_ERR)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_SAR3_ERR)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TEST_BLK_EN2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TXFE2_CLKDIV)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_SPARE1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TEST_BLK_EN4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_TXFE4_CLKDIV)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_3_4_SPARE2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_MODE_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_MODE_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_MODE_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_VCL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_VCL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_CCL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_CCL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_CCL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_CCL_4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_CTRL_CCL_5)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_BUCK_TMUX_A_D)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_BUCK_SW_DRV_CNTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_CLASSH_SPARE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_5)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_6)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_7)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_8)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEG_CTRL_9)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEGDAC_CTRL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEGDAC_CTRL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_VNEGDAC_CTRL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_CTRL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_FLYBACK_TEST_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_AUX_SW_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_PA_AUX_IN_CONN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_TIMER_DIV)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_OCP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_OCP_COUNT)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_EAR_DAC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_EAR_AMP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_HPH_LDO)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_HPH_PA)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_HPH_RDAC_LDO)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_HPH_CNP1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_HPH_LOWPOWER)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_AUX_DAC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_AUX_AMP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_VNEGDAC_BLEEDER)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_MISC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_BUCK_RST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_BUCK_VREF_ERRAMP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_FLYB_ERRAMP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_FLYB_BUFF)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_BIAS_FLYB_MID_RST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_L_STATUS)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_R_STATUS)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_CNP_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_CNP_WG_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_CNP_WG_TIME)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_OCP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_AUTO_CHOP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_CHOP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_PA_CTL1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_PA_CTL2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_L_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_L_TEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_L_ATEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_R_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_R_TEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_R_ATEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_RDAC_CLK_CTL1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_RDAC_CLK_CTL2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_RDAC_LDO_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_REFBUFF_UHQA_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_REFBUFF_LP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_L_DAC_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_R_DAC_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_SURGE_HPHLR_SURGE_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_EAR_EN_REG)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_EAR_PA_CON)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_EAR_SP_CON)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_EAR_DAC_CON)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_EAR_CNP_FSM_CON)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_TEST_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_STATUS_REG_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_STATUS_REG_2)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_ANA_NEW_PAGE_REGISTER)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_ANA_HPH2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_ANA_HPH3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_SLEEP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_SLEEP_WATCHDOG_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_PLUG_DETECT_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_ZDET_ANA_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_ZDET_RAMP_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_FSM_STATUS)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_ADC_RESULT)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_NEW_AMIC_MUX_CFG)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_AUXPA)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_CONFIG)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIE_CRACK_DIE_CRK_DET_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIE_CRACK_DIE_CRK_DET_OUT)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_VREF_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_PA_MISC1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_PA_MISC2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_PA_RDAC_MISC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_HPH_TIMER1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_HPH_TIMER2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_HPH_TIMER3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_HPH_TIMER4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_PA_RDAC_MISC2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_PA_RDAC_MISC3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_MBHC_NEW_INT_SPARE_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_INT_NEW_CNP_VCM_CON1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_INT_NEW_CNP_VCM_CON2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_EN_REG)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_PA_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_SP_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_DAC_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_CLK_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_TEST_CTRL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_STATUS_REG)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_AUX_INT_MISC)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_INT_BIAS)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_INT_STB_LOADS_DTEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_INT_TEST0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_INT_STARTUP_TIMER)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_INT_TEST1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_LDORXTX_INT_STATUS)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_SLEEP_INT_WATCHDOG_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_SLEEP_INT_WATCHDOG_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0)]=RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXADC_INT_L2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXADC_INT_L1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXADC_INT_L0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAGE_REGISTER)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CHIP_ID0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CHIP_ID1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CHIP_ID2)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CHIP_ID3)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_TX_CLK_RATE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_RST_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TOP_CLK_CFG)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_ANA_CLK_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DIG_CLK_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_RST_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_PATH_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_RX_RST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_RX0_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_RX1_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_RX2_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_COMP_CTL_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A1_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A1_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A2_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A2_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A3_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A3_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A4_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A4_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A5_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A5_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A6_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_A7_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_C_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_C_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_C_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_C_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R5)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R6)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_DSM_R7)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A1_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A1_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A2_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A2_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A3_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A3_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A4_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A4_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A5_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A5_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A6_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_A7_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_C_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_C_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_C_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_C_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R5)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R6)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_DSM_R7)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_HPH_GAIN_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AUX_GAIN_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_EAR_PATH_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_SWR_CLH)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_CLH_BYP)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX0_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX1_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX2_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX_RST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_REQ_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_RST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_AMIC_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC1_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC2_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC3_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC4_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_PRG_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC_RATE_1_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_DMIC_RATE_3_4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PDM_WD_CTL0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PDM_WD_CTL1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PDM_WD_CTL2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_MASK_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_MASK_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_MASK_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_STATUS_0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_STATUS_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_STATUS_2)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_CLEAR_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_CLEAR_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_CLEAR_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_LEVEL_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_LEVEL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_LEVEL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_SET_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_SET_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_SET_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_TEST_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_TEST_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_INTR_TEST_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_MODE_DBG_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_MODE_DBG_0_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_MODE_DBG_2_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_LB_IN_SEL_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_LOOP_BACK_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_DAC_TEST)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_RX_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_TX_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_RX_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_TX_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_TX_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SWR_HM_TEST_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_SWR_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_SWR_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_I2C_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_TEST_CTL_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_TEST_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_T_DATA_0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_T_DATA_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_PDM_RX0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_PDM_RX1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_PDM_TX0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_PDM_TX1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_CTL_PDM_TX2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_INP_DIS_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PAD_INP_DIS_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DRIVE_STRENGTH_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DRIVE_STRENGTH_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DRIVE_STRENGTH_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_RX_DATA_EDGE_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_DATA_EDGE_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_GPIO_MODE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PIN_CTL_OE)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PIN_CTL_DATA_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PIN_CTL_DATA_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PIN_STATUS_0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_PIN_STATUS_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DIG_DEBUG_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DIG_DEBUG_EN)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_ANA_CSR_DBG_ADD)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_ANA_CSR_DBG_CTL)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SSP_DBG)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_MODE_STATUS_0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_MODE_STATUS_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SPARE_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SPARE_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_SPARE_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_0)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_1)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_2)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_3)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_4)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_5)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_6)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_7)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_8)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_9)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_10)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_11)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_12)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_13)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_14)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_15)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_16)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_17)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_18)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_19)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_20)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_21)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_22)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_23)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_24)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_25)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_26)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_27)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_28)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_29)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_30)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_EFUSE_REG_31)] = RD_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_REQ_FB_CTL_0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_REQ_FB_CTL_1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_REQ_FB_CTL_2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_REQ_FB_CTL_3)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_TX_REQ_FB_CTL_4)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DEM_BYPASS_DATA0)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DEM_BYPASS_DATA1)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DEM_BYPASS_DATA2)] = RD_WR_REG,
|
||||||
|
[WCD938X_REG(WCD938X_DIGITAL_DEM_BYPASS_DATA3)] = RD_WR_REG,
|
||||||
|
};
|
||||||
2704
asoc/codecs/wcd938x/wcd938x.c
Normal file
2704
asoc/codecs/wcd938x/wcd938x.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user