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@@ -52,6 +52,10 @@
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#endif
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#include <linux/cpumask.h>
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+#if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE)
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+#include <pld_common.h>
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+#endif
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+
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void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t cmd_id, bool start)
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{
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hif_trigger_dump(hif_ctx, cmd_id, start);
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@@ -1043,6 +1047,7 @@ QDF_STATUS hif_try_prevent_ep_vote_access(struct hif_opaque_softc *hif_ctx)
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{
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struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
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uint32_t work_drain_wait_cnt = 0;
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+ uint32_t wait_cnt = 0;
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int work = 0;
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qdf_atomic_set(&scn->dp_ep_vote_access,
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@@ -1059,12 +1064,38 @@ QDF_STATUS hif_try_prevent_ep_vote_access(struct hif_opaque_softc *hif_ctx)
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hif_err("timeout wait for pending work %d ", work);
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return QDF_STATUS_E_FAULT;
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}
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+ qdf_sleep(10);
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+ }
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+
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+ while (pld_is_pci_ep_awake(scn->qdf_dev->dev)) {
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+ if (++wait_cnt > HIF_EP_WAKE_RESET_WAIT_CNT) {
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+ hif_err("Release EP vote is not proceed by Fw");
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+ return QDF_STATUS_E_FAULT;
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+ }
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qdf_sleep(5);
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}
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return QDF_STATUS_SUCCESS;
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}
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+void hif_set_ep_intermediate_vote_access(struct hif_opaque_softc *hif_ctx)
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+{
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+ struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
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+ uint8_t vote_access;
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+
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+ vote_access = qdf_atomic_read(&scn->ep_vote_access);
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+
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+ if (vote_access != HIF_EP_VOTE_ACCESS_DISABLE)
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+ hif_info("EP vote changed from:%u to intermediate state",
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+ vote_access);
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+
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+ if (QDF_IS_STATUS_ERROR(hif_try_prevent_ep_vote_access(hif_ctx)))
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+ QDF_BUG(0);
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+
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+ qdf_atomic_set(&scn->ep_vote_access,
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+ HIF_EP_VOTE_INTERMEDIATE_ACCESS);
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+}
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+
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void hif_allow_ep_vote_access(struct hif_opaque_softc *hif_ctx)
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{
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struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
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