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ipa: Remove is_hdr_proc_ctx flag

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The is_hdr_proc_ctx flag and the phys_base member were used
to add HPC instead of a header, if there is no memory space.
This logic was replaced by dynamic header distribution and
the members are not used anymore.
Removing all references in the code.

Change-Id: I1d4acda4882b4aeb892d2ab0ea03148c627dd630
Signed-off-by: Ilia Lin <quic_ilial@quicinc.com>
This commit is contained in:
Ilia Lin
2021-12-26 12:55:30 +02:00
parent 0e95bb3404
commit c8a0cc3c0a
6 changed files with 44 additions and 125 deletions
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31
drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
View File

@@ -776,26 +776,14 @@ static ssize_t ipa3_read_hdr(struct file *file, char __user *ubuf, size_t count,
nbytes = scnprintf(
dbg_buff,
IPA_MAX_MSG_LEN,
"name:%s len=%d ref=%d partial=%d type=%s ",
"name:%s len=%d ref=%d partial=%d type=%s ofst=%u ",
entry->name,
entry->hdr_len,
entry->ref_cnt,
entry->is_partial,
ipa3_hdr_l2_type_name[entry->type]);
if (entry->is_hdr_proc_ctx) {
nbytes += scnprintf(
dbg_buff + nbytes,
IPA_MAX_MSG_LEN - nbytes,
"phys_base=0x%pa ",
&entry->phys_base);
} else {
nbytes += scnprintf(
dbg_buff + nbytes,
IPA_MAX_MSG_LEN - nbytes,
"ofst=%u ",
ipa3_hdr_l2_type_name[entry->type],
entry->offset_entry->offset >> 2);
}
for (i = 0; i < entry->hdr_len; i++) {
scnprintf(dbg_buff + nbytes + i * 2,
IPA_MAX_MSG_LEN - nbytes - i * 2,
@@ -1288,18 +1276,6 @@ static ssize_t ipa3_read_proc_ctx(struct file *file, char __user *ubuf,
ofst_words = (entry->offset_entry->offset +
ipa3_ctx->hdr_proc_ctx_tbl.start_offset)
>> 5;
if (entry->hdr->is_hdr_proc_ctx) {
nbytes += scnprintf(dbg_buff + nbytes,
IPA_MAX_MSG_LEN - nbytes,
"id:%u hdr_proc_type:%s proc_ctx[32B]:%u ",
entry->id,
ipa3_hdr_proc_type_name[entry->type],
ofst_words);
nbytes += scnprintf(dbg_buff + nbytes,
IPA_MAX_MSG_LEN - nbytes,
"hdr_phys_base:0x%pa\n",
&entry->hdr->phys_base);
} else {
nbytes += scnprintf(dbg_buff + nbytes,
IPA_MAX_MSG_LEN - nbytes,
"id:%u hdr_proc_type:%s proc_ctx[32B]:%u ",
@@ -1311,7 +1287,6 @@ static ssize_t ipa3_read_proc_ctx(struct file *file, char __user *ubuf,
"hdr[words]:%u\n",
entry->hdr->offset_entry->offset >> 2);
}
}
mutex_unlock(&ipa3_ctx->lock);
return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes);

44
drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
View File

@@ -47,10 +47,7 @@ alloc:
return -ENOMEM;
}
list_for_each_entry(entry, &ipa3_ctx->hdr_tbl[loc].head_hdr_entry_list,
link) {
if (entry->is_hdr_proc_ctx)
continue;
list_for_each_entry(entry, &ipa3_ctx->hdr_tbl[loc].head_hdr_entry_list, link) {
IPADBG_LOW("hdr of len %d ofst=%d\n", entry->hdr_len,
entry->offset_entry->offset);
ipahal_cp_hdr_to_hw_buff(mem->base, entry->offset_entry->offset,
@@ -107,8 +104,6 @@ static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem,
ret = ipahal_cp_proc_ctx_to_hw_buff(entry->type, mem->base,
entry->offset_entry->offset,
entry->hdr->hdr_len,
entry->hdr->is_hdr_proc_ctx,
entry->hdr->phys_base,
(entry->hdr->is_lcl) ? hdr_lcl_addr : hdr_sys_addr,
entry->hdr->offset_entry,
&entry->l2tp_params,
@@ -441,8 +436,7 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx,
WARN_ON_RATELIMIT_IPA(1);
return -EINVAL;
}
IPADBG("Associated header is name=%s is_hdr_proc_ctx=%d\n",
hdr_entry->name, hdr_entry->is_hdr_proc_ctx);
IPADBG("Associated header is name=%s\n", hdr_entry->name);
entry = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_cache, GFP_KERNEL);
if (!entry) {
@@ -581,7 +575,6 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr, bool user,
entry->eth2_ofst = hdr->eth2_ofst;
entry->cookie = IPA_HDR_COOKIE;
entry->ipacm_installed = user;
entry->is_hdr_proc_ctx = false;
entry->is_lcl = ((IPA_MEM_PART(apps_hdr_size_ddr) &&
(entry->is_partial || (hdr->status == IPA_HDR_TO_DDR_PATTERN))) ||
!IPA_MEM_PART(apps_hdr_size)) ? false : true;
@@ -778,12 +771,7 @@ int __ipa3_del_hdr(u32 hdr_hdl, bool by_user)
htbl = entry->is_lcl ? &ipa3_ctx->hdr_tbl[HDR_TBL_LCL] : &ipa3_ctx->hdr_tbl[HDR_TBL_SYS];
if (entry->is_hdr_proc_ctx)
IPADBG("del hdr of len=%d hdr_cnt=%d phys_base=%pa\n",
entry->hdr_len, htbl->hdr_cnt, &entry->phys_base);
else
IPADBG("del hdr of len=%d hdr_cnt=%d ofst=%d\n",
entry->hdr_len, htbl->hdr_cnt,
IPADBG("del hdr of len=%d hdr_cnt=%d ofst=%d\n", entry->hdr_len, htbl->hdr_cnt,
entry->offset_entry->offset);
if (by_user && entry->user_deleted) {
@@ -809,17 +797,12 @@ int __ipa3_del_hdr(u32 hdr_hdl, bool by_user)
return 0;
}
if (entry->is_hdr_proc_ctx || entry->proc_ctx) {
dma_unmap_single(ipa3_ctx->pdev,
entry->phys_base,
entry->hdr_len,
DMA_TO_DEVICE);
if (entry->proc_ctx)
__ipa3_del_hdr_proc_ctx(entry->proc_ctx->id, false, false);
} else {
else
/* move the offset entry to appropriate free list */
list_move(&entry->offset_entry->link,
&htbl->head_free_offset_list[entry->offset_entry->bin]);
}
list_del(&entry->link);
htbl->hdr_cnt--;
entry->cookie = 0;
@@ -1257,12 +1240,6 @@ int ipa3_reset_hdr(bool user_only)
IPADBG("Trying to remove hdr %s offset=%u\n",
entry->name, entry->offset_entry->offset);
if (!entry->offset_entry->offset) {
if (entry->is_hdr_proc_ctx) {
IPAERR("default header is proc ctx\n");
mutex_unlock(&ipa3_ctx->lock);
WARN_ON_RATELIMIT_IPA(1);
return -EFAULT;
}
IPADBG("skip default header\n");
continue;
}
@@ -1276,20 +1253,17 @@ int ipa3_reset_hdr(bool user_only)
}
if (!user_only || entry->ipacm_installed) {
if (entry->is_hdr_proc_ctx) {
dma_unmap_single(ipa3_ctx->pdev,
entry->phys_base,
entry->hdr_len,
DMA_TO_DEVICE);
if (entry->proc_ctx) {
entry->proc_ctx->hdr = NULL;
entry->proc_ctx = NULL;
} else {
}
/* move the offset entry to free list */
entry->offset_entry->ipacm_installed = false;
list_move(&entry->offset_entry->link,
&ipa3_ctx->hdr_tbl[hdr_tbl_loc].head_free_offset_list[
entry->offset_entry->bin]);
}
/* delete the hdr entry from headers list */
list_del(&entry->link);
ipa3_ctx->hdr_tbl[hdr_tbl_loc].hdr_cnt--;
entry->ref_cnt = 0;

6
drivers/platform/msm/ipa/ipa_v3/ipa_i.h
View File

@@ -780,10 +780,6 @@ struct ipa3_rt_tbl {
* @name: name of header table entry
* @type: l2 header type
* @is_partial: flag indicating if header table entry is partial
* @is_hdr_proc_ctx: false - hdr entry resides in hdr table,
* true - hdr entry resides in DDR and pointed to by proc ctx
* @phys_base: physical address of entry in DDR when is_hdr_proc_ctx is true,
* else 0
* @proc_ctx: processing context header
* @offset_entry: entry's offset
* @cookie: cookie used for validity check
@@ -803,8 +799,6 @@ struct ipa3_hdr_entry {
char name[IPA_RESOURCE_NAME_MAX];
enum ipa_hdr_l2_type type;
u8 is_partial;
bool is_hdr_proc_ctx;
dma_addr_t phys_base;
struct ipa3_hdr_proc_ctx_entry *proc_ctx;
struct ipa_hdr_offset_entry *offset_entry;
u32 ref_cnt;

2
drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
View File

@@ -94,7 +94,7 @@ static int ipa_generate_rt_hw_rule(enum ipa_ip_type ip,
}
}
if (entry->proc_ctx || (entry->hdr && entry->hdr->is_hdr_proc_ctx)) {
if (entry->proc_ctx) {
struct ipa3_hdr_proc_ctx_entry *proc_ctx;
proc_ctx = (entry->proc_ctx) ? : entry->hdr->proc_ctx;

51
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
View File

@@ -1739,8 +1739,6 @@ static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset,
* @base: dma base address
* @offset: offset from base address where the data will be copied
* @hdr_len: the length of the header
* @is_hdr_proc_ctx: header is located in phys_base (true) or hdr_base_addr
* @phys_base: memory location in DDR
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
* @l2tp_params: l2tp parameters
@@ -1750,8 +1748,7 @@ static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset,
*/
static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
void *const base, u32 offset,
u32 hdr_len, bool is_hdr_proc_ctx,
dma_addr_t phys_base, u64 hdr_base_addr,
u32 hdr_len, u64 hdr_base_addr,
struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
struct ipa_eogre_hdr_proc_ctx_params *eogre_params,
@@ -1768,8 +1765,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx\n",
hdr_addr);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -1788,8 +1784,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx\n",
hdr_addr);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -1825,8 +1820,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx length %d\n",
hdr_addr, ctx->hdr_add.tlv.value);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -1866,8 +1860,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.length = 2;
if (l2tp_params->hdr_remove_param.eth_hdr_retained) {
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx length %d\n",
hdr_addr, ctx->hdr_add.tlv.value);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -1910,8 +1903,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%x\n",
ctx->hdr_add.hdr_addr);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -1940,8 +1932,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx\n",
hdr_addr);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -1976,8 +1967,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx length %d\n",
hdr_addr, ctx->hdr_add.tlv.value);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(
@@ -2001,8 +1991,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
hdr_addr = hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx\n",
hdr_addr);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
@@ -2106,7 +2095,6 @@ struct ipahal_hdr_funcs {
int (*ipahal_cp_proc_ctx_to_hw_buff)(enum ipa_hdr_proc_type type,
void *const base, u32 offset, u32 hdr_len,
bool is_hdr_proc_ctx, dma_addr_t phys_base,
u64 hdr_base_addr,
struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
@@ -2174,8 +2162,6 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *const hdr,
* @base: dma base address
* @offset: offset from base address where the data will be copied
* @hdr_len: the length of the header
* @is_hdr_proc_ctx: header is located in phys_base (true) or hdr_base_addr
* @phys_base: memory location in DDR
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
* @l2tp_params: l2tp parameters
@@ -2185,7 +2171,6 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *const hdr,
*/
int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
void *const base, u32 offset, u32 hdr_len,
bool is_hdr_proc_ctx, dma_addr_t phys_base,
u64 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
struct ipa_eogre_hdr_proc_ctx_params *eogre_params,
@@ -2193,24 +2178,18 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
bool is_64)
{
IPAHAL_DBG(
"type %d, base %pK, offset %d, hdr_len %d, is_hdr_proc_ctx %d, hdr_base_addr %llu, offset_entry %pK, bool %d\n"
, type, base, offset, hdr_len, is_hdr_proc_ctx,
hdr_base_addr, offset_entry, is_64);
"type %d, base %pK, offset %d, hdr_len %d, hdr_base_addr %llu, offset_entry %pK, bool %d\n"
, type, base, offset, hdr_len, hdr_base_addr, offset_entry, is_64);
if (!base ||
(is_hdr_proc_ctx && !phys_base) ||
(!is_hdr_proc_ctx && !offset_entry) ||
(!is_hdr_proc_ctx && !hdr_base_addr)) {
if (!base || !offset_entry || !hdr_base_addr) {
IPAHAL_ERR(
"invalid input: hdr_len:%u phys_base:%pad hdr_base_addr:%llu is_hdr_proc_ctx:%d offset_entry:%pK\n"
, hdr_len, &phys_base, hdr_base_addr
, is_hdr_proc_ctx, offset_entry);
"invalid input: hdr_len:%u hdr_base_addr:%llu offset_entry:%pK\n",
hdr_len, hdr_base_addr, offset_entry);
return -EINVAL;
}
return hdr_funcs.ipahal_cp_proc_ctx_to_hw_buff(type, base, offset,
hdr_len, is_hdr_proc_ctx, phys_base,
hdr_base_addr, offset_entry, l2tp_params,
hdr_len, hdr_base_addr, offset_entry, l2tp_params,
eogre_params, generic_params, is_64);
}

3
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h
View File

@@ -753,8 +753,6 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *hdr, u32 hdr_len);
* @base: dma base address
* @offset: offset from base address where the data will be copied
* @hdr_len: the length of the header
* @is_hdr_proc_ctx: header is located in phys_base (true) or hdr_base_addr
* @phys_base: memory location in DDR
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
* @l2tp_params: l2tp parameters
@@ -764,7 +762,6 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *hdr, u32 hdr_len);
*/
int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
void *base, u32 offset, u32 hdr_len,
bool is_hdr_proc_ctx, dma_addr_t phys_base,
u64 hdr_base_addr,
struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,