qcacld-3.0: Update the prealloc DP descriptor types

Update the prealloc DP descriptor types.

Change-Id: I3de60876735e5aa37d80e9e698a86503b18574c1
CRs-Fixed: 3502612

components/dp/core/src/wlan_dp_prealloc.c

@@ -92,7 +92,7 @@ struct dp_consistent_prealloc {
  * @pages: multi page information storage
  */
 struct dp_multi_page_prealloc {
-	enum dp_desc_type desc_type;
+	enum qdf_dp_desc_type desc_type;
 	qdf_size_t element_size;
 	uint16_t element_num;
 	bool in_use;
@@ -349,49 +349,49 @@ static struct  dp_consistent_prealloc g_dp_consistent_allocs[] = {
 
 static struct  dp_multi_page_prealloc g_dp_multi_page_allocs[] = {
 	/* 4 TX DESC pools */
-	{DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
-	{DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
-	{DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
-	{DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_DESC_TYPE, TX_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
 
 	/* 4 Tx EXT DESC NON Cacheable pools */
-	{DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
+	{QDF_DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
 	 NON_CACHEABLE, { 0 } },
-	{DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
+	{QDF_DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
 	 NON_CACHEABLE, { 0 } },
-	{DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
+	{QDF_DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
 	 NON_CACHEABLE, { 0 } },
-	{DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
+	{QDF_DP_TX_EXT_DESC_TYPE, HAL_TX_EXT_DESC_WITH_META_DATA, 0, 0,
 	 NON_CACHEABLE, { 0 } },
 
 	/* 4 Tx EXT DESC Link Cacheable pools */
-	{DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0, 0,
-	 CACHEABLE, { 0 } },
-	{DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0, 0,
-	 CACHEABLE, { 0 } },
-	{DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0, 0,
-	 CACHEABLE, { 0 } },
-	{DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0, 0,
-	 CACHEABLE, { 0 } },
+	{QDF_DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0,
+	 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0,
+	 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0,
+	 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_EXT_DESC_LINK_TYPE, sizeof(struct dp_tx_ext_desc_elem_s), 0,
+	 0, CACHEABLE, { 0 } },
 
 	/* 4 TX TSO DESC pools */
-	{DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
-	{DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
-	{DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
-	{DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
+	{QDF_DP_TX_TSO_DESC_TYPE, TX_TSO_DESC_SIZE, 0, 0, CACHEABLE, { 0 } },
 
 	/* 4 TX TSO NUM SEG DESC pools */
-	{DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
+	{QDF_DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
 	 CACHEABLE, { 0 } },
-	{DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
+	{QDF_DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
 	 CACHEABLE, { 0 } },
-	{DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
+	{QDF_DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
 	 CACHEABLE, { 0 } },
-	{DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
+	{QDF_DP_TX_TSO_NUM_SEG_TYPE, TX_TSO_NUM_SEG_DESC_SIZE, 0, 0,
 	 CACHEABLE, { 0 } },
 
 	/* DP RX DESCs BUF pools */
-	{DP_RX_DESC_BUF_TYPE, sizeof(union dp_rx_desc_list_elem_t),
+	{QDF_DP_RX_DESC_BUF_TYPE, sizeof(union dp_rx_desc_list_elem_t),
 	 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE * WLAN_CFG_RXDMA_REFILL_RING_SIZE, 0,
 	 CACHEABLE, { 0 } },
 
@@ -399,23 +399,23 @@ static struct  dp_multi_page_prealloc g_dp_multi_page_allocs[] = {
 	/* no op */
 #else
 	/* 2 DP RX DESCs Status pools */
-	{DP_RX_DESC_STATUS_TYPE, sizeof(union dp_rx_desc_list_elem_t),
+	{QDF_DP_RX_DESC_STATUS_TYPE, sizeof(union dp_rx_desc_list_elem_t),
 	 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE + 1, 0, CACHEABLE, { 0 } },
-	{DP_RX_DESC_STATUS_TYPE, sizeof(union dp_rx_desc_list_elem_t),
+	{QDF_DP_RX_DESC_STATUS_TYPE, sizeof(union dp_rx_desc_list_elem_t),
 	 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE + 1, 0, CACHEABLE, { 0 } },
 #endif
 	/* DP HW Link DESCs pools */
-	{DP_HW_LINK_DESC_TYPE, HW_LINK_DESC_SIZE, NUM_HW_LINK_DESCS, 0,
-	NON_CACHEABLE, { 0 } },
+	{QDF_DP_HW_LINK_DESC_TYPE, HW_LINK_DESC_SIZE, NUM_HW_LINK_DESCS, 0,
+	 NON_CACHEABLE, { 0 } },
 #ifdef CONFIG_BERYLLIUM
-	{DP_HW_CC_SPT_PAGE_TYPE, qdf_page_size,
+	{QDF_DP_HW_CC_SPT_PAGE_TYPE, qdf_page_size,
 	 ((DP_TX_RX_DESC_MAX_NUM * sizeof(uint64_t)) / qdf_page_size),
 	 0, NON_CACHEABLE, { 0 } },
 #endif
 #ifdef FEATURE_DIRECT_LINK
-	{DP_TX_DIRECT_LINK_CE_BUF_TYPE, qdf_page_size,
+	{QDF_DP_TX_DIRECT_LINK_CE_BUF_TYPE, qdf_page_size,
 	 TX_DIRECT_LINK_CE_BUF_PAGES, 0, NON_CACHEABLE, { 0 } },
-	{DP_TX_DIRECT_LINK_BUF_TYPE, qdf_page_size,
+	{QDF_DP_TX_DIRECT_LINK_BUF_TYPE, qdf_page_size,
 	 TX_DIRECT_LINK_BUF_PAGES, 0, NON_CACHEABLE, { 0 } },
 #endif
 };
@@ -666,17 +666,17 @@ dp_update_mem_size_by_ring_type(struct wlan_dp_prealloc_cfg *cfg,
  */
 static void
 dp_update_num_elements_by_desc_type(struct wlan_dp_prealloc_cfg *cfg,
-				    enum dp_desc_type desc_type,
+				    enum qdf_dp_desc_type desc_type,
 				    uint16_t *num_elements)
 {
 	switch (desc_type) {
-	case DP_TX_DESC_TYPE:
+	case QDF_DP_TX_DESC_TYPE:
 		*num_elements = cfg->num_tx_desc;
 		return;
-	case DP_TX_EXT_DESC_TYPE:
-	case DP_TX_EXT_DESC_LINK_TYPE:
-	case DP_TX_TSO_DESC_TYPE:
-	case DP_TX_TSO_NUM_SEG_TYPE:
+	case QDF_DP_TX_EXT_DESC_TYPE:
+	case QDF_DP_TX_EXT_DESC_LINK_TYPE:
+	case QDF_DP_TX_TSO_DESC_TYPE:
+	case QDF_DP_TX_TSO_NUM_SEG_TYPE:
 		*num_elements = cfg->num_tx_ext_desc;
 		return;
 	default:

components/dp/core/src/wlan_dp_wfds.c

@@ -382,13 +382,13 @@ dp_wfds_get_desc_type_from_mem_arena(enum wlan_qmi_wfds_mem_arenas mem_arena)
 {
 	switch (mem_arena) {
 	case QMI_WFDS_MEM_ARENA_TX_BUFFERS:
-		return DP_TX_DIRECT_LINK_BUF_TYPE;
+		return QDF_DP_TX_DIRECT_LINK_BUF_TYPE;
 	case QMI_WFDS_MEM_ARENA_CE_TX_MSG_BUFFERS:
-		return DP_TX_DIRECT_LINK_CE_BUF_TYPE;
+		return QDF_DP_TX_DIRECT_LINK_CE_BUF_TYPE;
 	default:
 		dp_debug("No desc type for mem arena %d", mem_arena);
 		qdf_assert(0);
-		return DP_DESC_TYPE_MAX;
+		return QDF_DP_DESC_TYPE_MAX;
 	}
 }
 
@@ -413,7 +413,7 @@ dp_wfds_alloc_mem_arena(struct dp_direct_link_wfds_context *dl_wfds,
 
 	desc_type = dp_wfds_get_desc_type_from_mem_arena(mem_arena);
 
-	if (desc_type != DP_DESC_TYPE_MAX) {
+	if (desc_type != QDF_DP_DESC_TYPE_MAX) {
 		elem_per_page = qdf_page_size / entry_size;
 		num_pages = num_entries / elem_per_page;
 		if (num_entries % elem_per_page)