disp: msm: dsi: add check for any queued DSI CMDs before clock force update

During a force update of DSI clocks, the state of the byte and pclks are
toggled irrespective of the ref-count. This in addition with ASYNC
command wait can result in interrupt storm, if and when the clocks are
being toggled a previous command that was triggered using the ASYNC
wait flag fires an ISR. The interrupt status doesn't get cleared if
the ISR is being serviced with the clocks are off.

The change adds a check for pending queued commands before any force
update of DSI clocks.

Change-Id: I4ca60d0ad43767791255f00c9af8e99e74786097
Signed-off-by: Satya Rama Aditya Pinapala <[email protected]>
Signed-off-by: Rajeev Nandan <[email protected]>

msm/dsi/dsi_display.c

@@ -5381,7 +5381,22 @@ int dsi_display_splash_res_cleanup(struct  dsi_display *display)
 
 static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
 {
-	int rc = 0;
+	int rc = 0, i = 0;
+	struct dsi_display_ctrl *ctrl;
+
+	/*
+	 * The force update dsi clock, is the only clock update function that toggles the state of
+	 * DSI clocks without any ref count protection. With the addition of ASYNC command wait,
+	 * there is a need for adding a check for any queued waits before updating these clocks.
+	 */
+	display_for_each_ctrl(i, display) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || !(ctrl->ctrl->post_tx_queued))
+			continue;
+		flush_workqueue(display->post_cmd_tx_workq);
+		cancel_work_sync(&ctrl->ctrl->post_cmd_tx_work);
+		ctrl->ctrl->post_tx_queued = false;
+	}
 
 	rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);