asoc: wcd9378: change the tx clk scale for different swr clk

when swr clk is 48Mhz, the swr base clk and clk scale
should be 19.2Mhz and DIV4.
when swr clk is 96Mhz, the swr base clk and clk scale
should be 19.2Mhz and DIV2.

Change-Id: I5beda01b024946cd7b54785ecfab91e3d0edc94f
Signed-off-by: Yuhui Zhao <[email protected]>

asoc/codecs/wcd9378/internal.h

@@ -142,8 +142,10 @@ struct wcd9378_priv {
 	bool usbc_hs_status;
 	/* wcd to swr dmic notification */
 	bool notify_swr_dmic;
-	u8 swr_base_clk;
-	u8 swr_clk_scale;
+	u8 rx_swrclk;
+	u8 rx_clkscale;
+	u8 tx_swrclk;
+	u8 tx_clkscale;
 	struct blocking_notifier_head notifier;
 };
 

asoc/codecs/wcd9378/wcd9378.c

@@ -38,6 +38,7 @@
 #define SWR_BASECLK_22P5792MHZ   (0x04)
 
 #define SWR_CLKSCALE_DIV2        (0x02)
+#define SWR_CLKSCALE_DIV4        (0x03)
 
 #define ADC_MODE_VAL_HIFI     0x01
 #define ADC_MODE_VAL_NORMAL   0x03
@@ -301,12 +302,12 @@ static int wcd9378_swr_slvdev_datapath_control(struct device *dev,
 
 	if (path == RX_PATH) {
 		swr_dev = wcd9378->rx_swr_dev;
-		swr_clk = wcd9378->swr_base_clk;
-		clk_scale = wcd9378->swr_clk_scale;
+		swr_clk = wcd9378->rx_swrclk;
+		clk_scale = wcd9378->rx_clkscale;
 	} else {
 		swr_dev = wcd9378->tx_swr_dev;
-		swr_clk = SWR_BASECLK_19P2MHZ;
-		clk_scale = SWR_CLKSCALE_DIV2;
+		swr_clk = wcd9378->tx_swrclk;
+		clk_scale = wcd9378->tx_clkscale;
 	}
 
 	bank = (wcd9378_swr_slv_get_current_bank(swr_dev,
@@ -985,6 +986,32 @@ void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
 	}
 }
 
+static void wcd9378_get_swr_clk_val(
+			struct snd_soc_component *component,
+			int rate)
+{
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+
+	switch (rate) {
+	case SWR_CLK_RATE_4P8MHZ:
+		wcd9378->tx_swrclk = SWR_BASECLK_19P2MHZ;
+		wcd9378->tx_clkscale = SWR_CLKSCALE_DIV4;
+		break;
+	case SWR_CLK_RATE_9P6MHZ:
+		wcd9378->tx_swrclk = SWR_BASECLK_19P2MHZ;
+		wcd9378->tx_clkscale = SWR_CLKSCALE_DIV2;
+		break;
+	default:
+		dev_dbg(component->dev, "%s: unsupport rate: %d\n",
+				__func__, rate);
+		break;
+	}
+
+	dev_dbg(component->dev, "%s: rate: %d, tx_swrclk: 0x%x, tx_clkscale: 0x%x\n",
+		__func__, rate, wcd9378->tx_swrclk, wcd9378->tx_clkscale);
+}
+
 static int wcd9378_get_clk_rate(int mode)
 {
 	int rate;
@@ -1219,6 +1246,8 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 		wcd9378_tx_connect_port(component, w->shift, rate,
 				true);
 
+		wcd9378_get_swr_clk_val(component, rate);
+
 		switch (w->shift) {
 		case ADC1:
 			/*SMP MIC0 IT11 USAGE SET*/
@@ -1343,6 +1372,8 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 
 		switch (w->shift) {
 		case ADC1:
+			snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
+						WCD9378_IT11_USAGE_IT11_USAGE_MASK, 0x00);
 			/*Normal TXFE Startup*/
 			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
 					WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
@@ -1353,12 +1384,22 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 
 			break;
 		case ADC2:
-			if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
+			if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status)) {
+				snd_soc_component_update_bits(component,
+						WCD9378_IT31_USAGE,
+						WCD9378_IT31_USAGE_IT31_USAGE_MASK, 0x00);
+
 				/*tear down TX1 sequencer*/
 				snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
 						WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
+			}
 
 			if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status)) {
+				snd_soc_component_update_bits(component,
+						WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
+						WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
+						0x00);
+
 				/*Normal TXFE Startup*/
 				snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
 						WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
@@ -1371,6 +1412,11 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 			}
 			break;
 		case ADC3:
+			snd_soc_component_update_bits(component,
+						WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
+						WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
+						0x00);
+
 			/*Normal TXFE Startup*/
 			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
 					WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
@@ -2504,20 +2550,20 @@ static int wcd9378_event_notify(struct notifier_block *block,
 
 		switch (rx_clk_type) {
 		case RX_CLK_12P288MHZ:
-			wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
-			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			wcd9378->rx_swrclk = SWR_BASECLK_24P576MHZ;
+			wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
 			break;
 		case RX_CLK_11P2896MHZ:
-			wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
-			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			wcd9378->rx_swrclk = SWR_BASECLK_22P5792MHZ;
+			wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
 			break;
 		default:
-			wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
-			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			wcd9378->rx_swrclk = SWR_BASECLK_19P2MHZ;
+			wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
 			break;
 		}
 		dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
-				__func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
+				__func__, wcd9378->rx_swrclk, wcd9378->rx_clkscale);
 
 		break;
 	default: