video: driver: fix queuing too many output buffers to firmware
Client is setting NV12 fmt as OP format before initial reconfig So during input port stream_on, subscribe_input_property is failing due to ubwc check(NV12 fmt), so DPB_LIST cap is getting disabled, but later client is setting NV12C during reconfig. So msm_vdec_release_nonref_buffers() during qbuf is bypassed and release cmd is never sent to fw for pending ro buffers. Infact entire RO handling at driver side is disabled. Looks like due to some reason client was not requeueing same buffers at same slot, So eventually number of pending RO buffers increasing over the time. Once count shoots more than 256 fw assertion happens and i.e leading to system error. Remove UBWC check while subscribing input port properties, so DPB_LIST willbe subscribed always and avoids above mentioned issues. Change-Id: I57ea0ea637ae3a57fcad430b212dcdb10f8e6d0f Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
此提交包含在:
@@ -1729,12 +1729,6 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
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V4L2_CID_MPEG_VIDC_ENC_INPUT_COMPRESSION_RATIO,
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0, CAP_FLAG_DYNAMIC_ALLOWED},
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{DPB_LIST, DEC, CODECS_ALL,
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0, 1, 1, 0,
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0,
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HFI_PROP_DPB_LIST,
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CAP_FLAG_INPUT_PORT},
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{FILM_GRAIN, DEC, AV1,
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0, 1, 1, 0,
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V4L2_CID_MPEG_VIDC_AV1D_FILM_GRAIN_PRESENT,
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@@ -2615,11 +2609,6 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_pine
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NULL,
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msm_vidc_set_reserve_duration},
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{DPB_LIST, DEC, CODECS_ALL,
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{0},
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NULL,
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NULL},
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{DRAP, DEC, AV1,
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{0},
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NULL,
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@@ -1269,12 +1269,6 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
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{FIRMWARE_PRIORITY_OFFSET, DEC | ENC, CODECS_ALL,
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1, 1, 1, 1},
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{DPB_LIST, DEC, CODECS_ALL,
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0, 1, 1, 0,
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0,
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HFI_PROP_DPB_LIST,
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CAP_FLAG_OUTPUT_PORT},
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{ALL_INTRA, ENC, H264|HEVC,
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0, 1, 1, 0,
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0,
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@@ -1685,11 +1679,6 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_pine
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NULL,
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NULL},
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{DPB_LIST, DEC, CODECS_ALL,
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{0},
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NULL,
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NULL},
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{ALL_INTRA, ENC, H264|HEVC,
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{LTR_COUNT, SLICE_MODE, BIT_RATE},
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msm_vidc_adjust_all_intra,
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