disp: msm: add VDC topology related changes
Add support to configure the DPU pipeline to support VDC-m topologies. Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Cette révision appartient à :
Abhinav Kumar
révisé par
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
Parent
d88b5b5c67
révision
c4f5050e13
@@ -20,10 +20,12 @@
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#include "sde_encoder_phys.h"
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#include "sde_power_handle.h"
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#include "sde_hw_dsc.h"
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#include "sde_hw_vdc.h"
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#include "sde_crtc.h"
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#include "sde_trace.h"
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#include "sde_core_irq.h"
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#include "sde_dsc_helper.h"
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#include "sde_vdc_helper.h"
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#define SDE_DEBUG_DCE(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
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(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
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@@ -65,7 +67,7 @@ static int _dce_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
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}
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if ((pic_width % dsc->config.slice_width) ||
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(pic_height % dsc->config.slice_height)) {
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(pic_height % dsc->config.slice_height)) {
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SDE_ERROR("pic_dim=%dx%d has to be multiple of slice=%dx%d\n",
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pic_width, pic_height,
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dsc->config.slice_width, dsc->config.slice_height);
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@@ -78,6 +80,29 @@ static int _dce_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
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return 0;
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}
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static int _dce_vdc_update_pic_dim(struct msm_display_vdc_info *vdc,
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int frame_width, int frame_height)
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{
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if (!vdc || !frame_width || !frame_height) {
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SDE_ERROR("invalid input: frame_width=%d frame_height=%d\n",
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frame_width, frame_height);
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return -EINVAL;
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}
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if ((frame_width % vdc->slice_width) ||
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(frame_height % vdc->slice_height)) {
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SDE_ERROR("pic_dim=%dx%d has to be multiple of slice=%dx%d\n",
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frame_width, frame_height,
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vdc->slice_width, vdc->slice_height);
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return -EINVAL;
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}
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vdc->frame_width = frame_width;
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vdc->frame_height = frame_height;
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return 0;
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}
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static int _dce_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
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int enc_ip_width,
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int dsc_cmn_mode)
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@@ -223,24 +248,59 @@ static void _dce_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
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hw_dsc_pp->ops.enable_dsc(hw_dsc_pp);
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}
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static inline bool _dce_check_half_panel_update(int num_dsc,
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bool merge_3d,
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static void _dce_vdc_pipe_cfg(struct sde_hw_vdc *hw_vdc,
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struct sde_hw_pingpong *hw_pp,
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struct msm_display_vdc_info *vdc,
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enum sde_3d_blend_mode mode_3d,
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bool disable_merge_3d, bool enable)
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{
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if (!vdc || !hw_vdc || !hw_pp) {
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SDE_ERROR("invalid params %d %d %d\n", !vdc, !hw_vdc,
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!hw_pp);
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return;
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}
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if (!enable) {
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if (hw_vdc->ops.vdc_disable)
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hw_vdc->ops.vdc_disable(hw_vdc);
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if (hw_vdc->ops.bind_pingpong_blk)
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hw_vdc->ops.bind_pingpong_blk(hw_vdc, false,
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PINGPONG_MAX);
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if (mode_3d && hw_pp->ops.reset_3d_mode)
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hw_pp->ops.reset_3d_mode(hw_pp);
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return;
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}
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if (hw_vdc->ops.vdc_config)
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hw_vdc->ops.vdc_config(hw_vdc, vdc);
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if (mode_3d && disable_merge_3d && hw_pp->ops.reset_3d_mode) {
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SDE_DEBUG("disabling 3d mux\n");
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hw_pp->ops.reset_3d_mode(hw_pp);
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}
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if (mode_3d && !disable_merge_3d && hw_pp->ops.setup_3d_mode) {
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SDE_DEBUG("enabling 3d mux\n");
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hw_pp->ops.setup_3d_mode(hw_pp, mode_3d);
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}
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if (hw_vdc->ops.bind_pingpong_blk)
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hw_vdc->ops.bind_pingpong_blk(hw_vdc, true, hw_pp->idx);
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}
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static inline bool _dce_check_half_panel_update(int num_lm,
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unsigned long affected_displays)
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{
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/**
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* partial update logic is currently supported only upto dual
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* pipe configurations.
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*/
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if (merge_3d) {
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int num_mixers = 2;
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return (hweight_long(affected_displays) != num_mixers);
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} else if (num_dsc > 1) {
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return (hweight_long(affected_displays) != num_dsc);
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}
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return false;
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return (hweight_long(affected_displays) != num_lm);
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}
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static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
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struct sde_encoder_kickoff_params *params)
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{
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@@ -263,7 +323,7 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
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bool disable_merge_3d = false;
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int this_frame_slices;
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int intf_ip_w, enc_ip_w;
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int num_intf, num_dsc;
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int num_intf, num_dsc, num_lm;
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int ich_res;
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int dsc_common_mode = 0;
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int i;
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@@ -314,6 +374,7 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
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num_intf = def->num_intf;
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mode_3d = (topology == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC) ?
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BLEND_3D_H_ROW_INT : BLEND_3D_NONE;
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num_lm = def->num_lm;
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/*
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* If this encoder is driving more than one DSC encoder, they
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@@ -323,9 +384,8 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
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_dce_dsc_update_pic_dim(dsc, roi->w, roi->h);
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merge_3d = (mode_3d != BLEND_3D_NONE) ? true: false;
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dsc_merge = (num_dsc > num_intf) ? true : false;
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half_panel_partial_update = _dce_check_half_panel_update(
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num_dsc, merge_3d, params->affected_displays);
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half_panel_partial_update = _dce_check_half_panel_update(num_lm,
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params->affected_displays);
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if (half_panel_partial_update && merge_3d)
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disable_merge_3d = true;
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@@ -445,6 +505,176 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
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return 0;
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}
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static int _dce_vdc_setup(struct sde_encoder_virt *sde_enc,
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struct sde_encoder_kickoff_params *params)
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{
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struct drm_connector *drm_conn;
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struct sde_kms *sde_kms;
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struct msm_drm_private *priv;
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struct drm_encoder *drm_enc;
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struct sde_encoder_phys *enc_master;
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struct sde_hw_vdc *hw_vdc[MAX_CHANNELS_PER_ENC];
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struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
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struct msm_display_vdc_info *vdc = NULL;
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enum sde_rm_topology_name topology;
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const struct sde_rect *roi;
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struct sde_hw_ctl *hw_ctl;
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struct sde_hw_intf_cfg_v1 cfg;
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enum sde_3d_blend_mode mode_3d;
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bool half_panel_partial_update, merge_3d;
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bool disable_merge_3d = false;
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int this_frame_slices;
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int intf_ip_w, enc_ip_w;
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const struct sde_rm_topology_def *def;
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int num_intf, num_vdc, num_lm;
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int i;
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int ret = 0;
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if (!sde_enc || !params || !sde_enc->phys_encs[0] ||
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!sde_enc->phys_encs[0]->connector)
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return -EINVAL;
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drm_conn = sde_enc->phys_encs[0]->connector;
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topology = sde_connector_get_topology_name(drm_conn);
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if (topology == SDE_RM_TOPOLOGY_NONE) {
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SDE_ERROR_DCE(sde_enc, "topology not set yet\n");
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return -EINVAL;
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}
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SDE_DEBUG_DCE(sde_enc, "topology:%d\n", topology);
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SDE_EVT32(DRMID(&sde_enc->base), topology,
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sde_enc->cur_conn_roi.x,
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sde_enc->cur_conn_roi.y,
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sde_enc->cur_conn_roi.w,
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sde_enc->cur_conn_roi.h,
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sde_enc->prv_conn_roi.x,
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sde_enc->prv_conn_roi.y,
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sde_enc->prv_conn_roi.w,
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sde_enc->prv_conn_roi.h,
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sde_enc->cur_master->cached_mode.hdisplay,
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sde_enc->cur_master->cached_mode.vdisplay);
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if (sde_kms_rect_is_equal(&sde_enc->cur_conn_roi,
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&sde_enc->prv_conn_roi))
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return ret;
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enc_master = sde_enc->cur_master;
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roi = &sde_enc->cur_conn_roi;
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hw_ctl = enc_master->hw_ctl;
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vdc = &sde_enc->mode_info.comp_info.vdc_info;
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drm_enc = &sde_enc->base;
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priv = drm_enc->dev->dev_private;
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sde_kms = to_sde_kms(priv->kms);
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def = sde_rm_topology_get_topology_def(&sde_kms->rm, topology);
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if (IS_ERR_OR_NULL(def))
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return -EINVAL;
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num_vdc = def->num_comp_enc;
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num_intf = def->num_intf;
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mode_3d = (topology == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC) ?
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BLEND_3D_H_ROW_INT : BLEND_3D_NONE;
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num_lm = def->num_lm;
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/*
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* If this encoder is driving more than one VDC encoder, they
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* operate in tandem, same pic dimension needs to be used by
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* each of them.(pp-split is assumed to be not supported)
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*/
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_dce_vdc_update_pic_dim(vdc, roi->w, roi->h);
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merge_3d = (mode_3d != BLEND_3D_NONE) ? true : false;
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half_panel_partial_update = _dce_check_half_panel_update(num_lm,
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params->affected_displays);
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if (half_panel_partial_update && merge_3d)
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disable_merge_3d = true;
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this_frame_slices = roi->w / vdc->slice_width;
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intf_ip_w = this_frame_slices * vdc->slice_width;
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sde_vdc_populate_config(vdc, intf_ip_w, vdc->traffic_mode);
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enc_ip_w = intf_ip_w;
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SDE_DEBUG_DCE(sde_enc, "pic_w: %d pic_h: %d\n",
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roi->w, roi->h);
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for (i = 0; i < num_vdc; i++) {
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bool active = !!((1 << i) & params->affected_displays);
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/*
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* if half_panel partial update vdc should be bound to the pp
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* that is driving the update, in other case when both the
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* layer mixers are driving the update, vdc should be bound
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* to left side pp
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*/
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if (merge_3d && half_panel_partial_update)
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hw_pp[i] = (active) ? sde_enc->hw_pp[0] :
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sde_enc->hw_pp[1];
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else
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hw_pp[i] = sde_enc->hw_pp[i];
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hw_vdc[i] = sde_enc->hw_vdc[i];
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if (!hw_vdc[i]) {
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SDE_ERROR_DCE(sde_enc, "invalid params for VDC\n");
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SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h,
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i, active);
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return -EINVAL;
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}
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_dce_vdc_pipe_cfg(hw_vdc[i], hw_pp[i],
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vdc, mode_3d, disable_merge_3d, active);
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memset(&cfg, 0, sizeof(cfg));
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cfg.vdc[cfg.vdc_count++] = hw_vdc[i]->idx;
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if (hw_ctl->ops.update_intf_cfg)
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hw_ctl->ops.update_intf_cfg(hw_ctl,
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&cfg,
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active);
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if (hw_ctl->ops.update_bitmask_vdc)
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hw_ctl->ops.update_bitmask_vdc(hw_ctl,
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hw_vdc[i]->idx, active);
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SDE_DEBUG_DCE(sde_enc,
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"update_intf_cfg hw_ctl[%d], vdc:%d, %s",
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hw_ctl->idx,
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cfg.vdc[0],
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active ? "enabled" : "disabled");
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if (mode_3d) {
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memset(&cfg, 0, sizeof(cfg));
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cfg.merge_3d[cfg.merge_3d_count++] =
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hw_pp[i]->merge_3d->idx;
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if (hw_ctl->ops.update_intf_cfg)
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hw_ctl->ops.update_intf_cfg(hw_ctl,
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&cfg,
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!disable_merge_3d);
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if (hw_ctl->ops.update_bitmask_merge3d)
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hw_ctl->ops.update_bitmask_merge3d(
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hw_ctl,
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hw_pp[i]->merge_3d->idx, true);
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SDE_DEBUG("mode_3d %s, on CTL_%d PP-%d merge3d:%d\n",
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disable_merge_3d ?
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"disabled" : "enabled",
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hw_ctl->idx - CTL_0,
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hw_pp[i]->idx - PINGPONG_0,
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hw_pp[i]->merge_3d ?
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hw_pp[i]->merge_3d->idx - MERGE_3D_0 :
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-1);
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}
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}
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return 0;
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}
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static void _dce_dsc_disable(struct sde_encoder_virt *sde_enc)
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{
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int i;
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@@ -494,7 +724,55 @@ static void _dce_dsc_disable(struct sde_encoder_virt *sde_enc)
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*/
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}
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static bool _dce_dsc_is_dirty(struct sde_encoder_virt *sde_enc)
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static void _dce_vdc_disable(struct sde_encoder_virt *sde_enc)
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{
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int i;
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struct sde_hw_pingpong *hw_pp = NULL;
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struct sde_hw_vdc *hw_vdc = NULL;
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struct sde_hw_ctl *hw_ctl = NULL;
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struct sde_hw_intf_cfg_v1 cfg;
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if (!sde_enc || !sde_enc->phys_encs[0] ||
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!sde_enc->phys_encs[0]->connector) {
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SDE_ERROR("invalid params %d %d\n",
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!sde_enc, sde_enc ? !sde_enc->phys_encs[0] : -1);
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return;
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}
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if (sde_enc->cur_master)
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hw_ctl = sde_enc->cur_master->hw_ctl;
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memset(&cfg, 0, sizeof(cfg));
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/* Disable VDC for all the pp's present in this topology */
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
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hw_pp = sde_enc->hw_pp[i];
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hw_vdc = sde_enc->hw_vdc[i];
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_dce_vdc_pipe_cfg(hw_vdc, hw_pp, NULL,
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BLEND_3D_NONE, false,
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false);
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if (hw_vdc) {
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sde_enc->dirty_vdc_ids[i] = hw_vdc->idx;
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cfg.vdc[cfg.vdc_count++] = hw_vdc->idx;
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}
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}
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/* Clear the VDC ACTIVE config for this CTL */
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if (hw_ctl && hw_ctl->ops.update_intf_cfg)
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hw_ctl->ops.update_intf_cfg(hw_ctl, &cfg, false);
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/**
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* Since pending flushes from previous commit get cleared
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* sometime after this point, setting VDC flush bits now
|
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* will have no effect. Therefore dirty_vdc_ids track which
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* VDC blocks must be flushed for the next trigger.
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*/
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}
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bool _dce_dsc_is_dirty(struct sde_encoder_virt *sde_enc)
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{
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int i;
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@@ -510,6 +788,21 @@ static bool _dce_dsc_is_dirty(struct sde_encoder_virt *sde_enc)
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return false;
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}
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bool _dce_vdc_is_dirty(struct sde_encoder_virt *sde_enc)
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{
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int i;
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
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/**
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* This dirty_vdc_hw field is set during VDC disable to
|
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* indicate which VDC blocks need to be flushed
|
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*/
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if (sde_enc->dirty_vdc_ids[i])
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return true;
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}
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return false;
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}
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static void _dce_helper_flush_dsc(struct sde_encoder_virt *sde_enc)
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{
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@@ -529,6 +822,24 @@ static void _dce_helper_flush_dsc(struct sde_encoder_virt *sde_enc)
|
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}
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}
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void _dce_helper_flush_vdc(struct sde_encoder_virt *sde_enc)
|
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{
|
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int i;
|
||||
struct sde_hw_ctl *hw_ctl = NULL;
|
||||
enum sde_vdc vdc_idx;
|
||||
|
||||
if (sde_enc->cur_master)
|
||||
hw_ctl = sde_enc->cur_master->hw_ctl;
|
||||
|
||||
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
|
||||
vdc_idx = sde_enc->dirty_vdc_ids[i];
|
||||
if (vdc_idx && hw_ctl && hw_ctl->ops.update_bitmask_vdc)
|
||||
hw_ctl->ops.update_bitmask_vdc(hw_ctl, vdc_idx, 1);
|
||||
|
||||
sde_enc->dirty_vdc_ids[i] = VDC_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
void sde_encoder_dce_disable(struct sde_encoder_virt *sde_enc)
|
||||
{
|
||||
enum msm_display_compression_type comp_type;
|
||||
@@ -540,6 +851,8 @@ void sde_encoder_dce_disable(struct sde_encoder_virt *sde_enc)
|
||||
|
||||
if (comp_type == MSM_DISPLAY_COMPRESSION_DSC)
|
||||
_dce_dsc_disable(sde_enc);
|
||||
else if (comp_type == MSM_DISPLAY_COMPRESSION_VDC)
|
||||
_dce_vdc_disable(sde_enc);
|
||||
}
|
||||
|
||||
int sde_encoder_dce_flush(struct sde_encoder_virt *sde_enc)
|
||||
@@ -551,6 +864,8 @@ int sde_encoder_dce_flush(struct sde_encoder_virt *sde_enc)
|
||||
|
||||
if (_dce_dsc_is_dirty(sde_enc))
|
||||
_dce_helper_flush_dsc(sde_enc);
|
||||
else if (_dce_vdc_is_dirty(sde_enc))
|
||||
_dce_helper_flush_vdc(sde_enc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
@@ -568,6 +883,8 @@ int sde_encoder_dce_setup(struct sde_encoder_virt *sde_enc,
|
||||
|
||||
if (comp_type == MSM_DISPLAY_COMPRESSION_DSC)
|
||||
rc = _dce_dsc_setup(sde_enc, params);
|
||||
else if (comp_type == MSM_DISPLAY_COMPRESSION_VDC)
|
||||
rc = _dce_vdc_setup(sde_enc, params);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
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