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qcacmn: Rx path changes for multichip MLO

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Rx patch changes for multichip MLO

1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
   on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
   to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
   SOC of reo ring

Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
This commit is contained in:
Chaithanya Garrepalli
2021-11-23 15:34:30 +05:30
committed by Madan Koyyalamudi
parent bbe062b4b7
commit c42af1f62f
23 changed files with 658 additions and 57 deletions
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73
hal/wifi3.0/be/hal_be_generic_api.c
View File

@@ -24,14 +24,19 @@
#include "hal_tx.h" //HAL_SET_FLD
#include "hal_be_rx.h" //HAL_RX_BUF_RBM_GET
#if defined(QDF_BIG_ENDIAN_MACHINE)
/**
* hal_setup_reo_swap() - Set the swap flag for big endian machines
* @soc: HAL soc handle
/*
* The 4 bits REO destination ring value is defined as: 0: TCL
* 1:SW1 2:SW2 3:SW3 4:SW4 5:Release 6:FW(WIFI) 7:SW5
* 8:SW6 9:SW7 10:SW8 11: NOT_USED.
*
* Return: None
*/
static void hal_setup_reo_swap(struct hal_soc *soc)
uint32_t reo_dest_ring_remap[] = {REO_REMAP_SW1, REO_REMAP_SW2,
REO_REMAP_SW3, REO_REMAP_SW4,
REO_REMAP_SW5, REO_REMAP_SW6,
REO_REMAP_SW7, REO_REMAP_SW8};
#if defined(QDF_BIG_ENDIAN_MACHINE)
void hal_setup_reo_swap(struct hal_soc *soc)
{
uint32_t reg_val;
@@ -45,7 +50,7 @@ static void hal_setup_reo_swap(struct hal_soc *soc)
REO_REG_REG_BASE), reg_val);
}
#else
static inline void hal_setup_reo_swap(struct hal_soc *soc)
void hal_setup_reo_swap(struct hal_soc *soc)
{
}
#endif
@@ -891,6 +896,60 @@ uint32_t hal_rx_msdu_reo_dst_ind_get_be(hal_soc_handle_t hal_soc_hdl,
return dst_ind;
}
uint32_t
hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl,
uint8_t rx_ring_mask)
{
uint32_t num_rings = 0;
uint32_t i = 0;
uint32_t ring_remap_arr[HAL_MAX_REO2SW_RINGS] = {0};
uint32_t reo_remap_val = 0;
uint32_t ring_idx = 0;
uint8_t ix_map[HAL_NUM_RX_RING_PER_IX_MAP] = {0};
/* create reo ring remap array */
while (i < HAL_MAX_REO2SW_RINGS) {
if (rx_ring_mask & (1 << i)) {
ring_remap_arr[num_rings] = reo_dest_ring_remap[i];
num_rings++;
}
i++;
}
for (i = 0; i < HAL_NUM_RX_RING_PER_IX_MAP; i++) {
if (rx_ring_mask) {
ix_map[i] = ring_remap_arr[ring_idx];
ring_idx = ((ring_idx + 1) % num_rings);
} else {
/* if ring mask is zero configure to release to WBM */
ix_map[i] = REO_REMAP_RELEASE;
}
}
reo_remap_val = HAL_REO_REMAP_IX0(ix_map[0], 0) |
HAL_REO_REMAP_IX0(ix_map[1], 1) |
HAL_REO_REMAP_IX0(ix_map[2], 2) |
HAL_REO_REMAP_IX0(ix_map[3], 3) |
HAL_REO_REMAP_IX0(ix_map[4], 4) |
HAL_REO_REMAP_IX0(ix_map[5], 5) |
HAL_REO_REMAP_IX0(ix_map[6], 6) |
HAL_REO_REMAP_IX0(ix_map[7], 7);
return reo_remap_val;
}
qdf_export_symbol(hal_reo_ix_remap_value_get_be);
uint8_t hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id)
{
if (rx_ring_id > HAL_MAX_REO2SW_RINGS)
return REO_REMAP_RELEASE;
return reo_dest_ring_remap[rx_ring_id];
}
qdf_export_symbol(hal_reo_ring_remap_value_get_be);
/**
* hal_hw_txrx_default_ops_attach_be() - Attach the default hal ops for
* beryllium chipsets.