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@@ -399,6 +399,14 @@ static struct msm_platform_inst_capability instance_cap_data_anorak[] = {
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR},
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+ {VUI_TIMING_INFO, ENC, CODECS_ALL,
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+ V4L2_MPEG_MSM_VIDC_DISABLE,
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+ V4L2_MPEG_MSM_VIDC_ENABLE,
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+ 1, V4L2_MPEG_MSM_VIDC_DISABLE,
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+ V4L2_CID_MPEG_VIDC_VUI_TIMING_INFO,
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+ HFI_PROP_DISABLE_VUI_TIMING_INFO,
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+ CAP_FLAG_OUTPUT_PORT},
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+
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{WITHOUT_STARTCODE, ENC, CODECS_ALL,
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V4L2_MPEG_MSM_VIDC_DISABLE,
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V4L2_MPEG_MSM_VIDC_ENABLE,
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@@ -485,6 +493,9 @@ static struct msm_platform_inst_capability instance_cap_data_anorak[] = {
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{LOWLATENCY_MAX_BITRATE, ENC, H264|HEVC, 0,
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70000000, 1, 70000000},
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+ {NUM_COMV, DEC, CODECS_ALL,
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+ 0, INT_MAX, 1, 0},
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+
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{LOSSLESS, ENC, HEVC,
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V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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@@ -1443,6 +1454,11 @@ static struct msm_platform_inst_capability instance_cap_data_anorak[] = {
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HFI_PROP_AV1_DRAP_CONFIG,
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CAP_FLAG_INPUT_PORT},
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+ {LAST_FLAG_EVENT_ENABLE, DEC, CODECS_ALL,
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+ V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
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+ 1, V4L2_MPEG_MSM_VIDC_DISABLE,
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+ V4L2_CID_MPEG_VIDC_LAST_FLAG_EVENT_ENABLE},
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+
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{META_BITSTREAM_RESOLUTION, DEC, AV1,
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V4L2_MPEG_VIDC_META_DISABLE,
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V4L2_MPEG_VIDC_META_ENABLE | V4L2_MPEG_VIDC_META_RX_INPUT |
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@@ -2406,6 +2422,12 @@ static struct msm_platform_inst_cap_dependency instance_cap_dependency_data_anor
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{SLICE_MODE}, {LOWLATENCY_MODE, OUTPUT_BUF_HOST_MAX_COUNT},
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msm_vidc_adjust_delivery_mode,
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msm_vidc_set_u32},
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+
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+ {VUI_TIMING_INFO, ENC, CODECS_ALL,
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+ {0},
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+ {0},
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+ NULL,
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+ msm_vidc_set_vui_timing_info},
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};
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/* Default UBWC config for LPDDR5 */
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