From 1e60728ab8c0b08ace93ce4692d1f4c6fb238c5f Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 23 Oct 2019 17:00:52 +0530 Subject: [PATCH] disp: msm: sde: Fix 32-bit compilation issues 1.Typecast to avoid distinct pointer type comparison 2.Keep DMA mask aligned with api definition. 3.Add Suffix for literals 4.Remove multfrac func to avoid uncompatible division. 5.64-bit division( operator "/") on 32-bit platforms is not supported. Using platform independent API's here Change-Id: I0e7305418e53876bd1adf00c1963f85cbdf980cc Signed-off-by: Ravikanth Tuniki --- msm/dsi/dsi_ctrl.c | 4 ++-- msm/dsi/dsi_panel.c | 30 +++++++++++++++++++----------- msm/dsi/dsi_phy_timing_v4_0.c | 6 +++--- msm/msm_smmu.c | 2 +- msm/sde/sde_crtc.c | 4 ++-- msm/sde_power_handle.h | 4 ++-- pll/dsi_pll.h | 4 ++-- pll/dsi_pll_14nm_util.c | 5 +++-- pll/dsi_pll_7nm.c | 12 ++++++------ rotator/sde_rotator_smmu.c | 2 +- 10 files changed, 41 insertions(+), 32 deletions(-) diff --git a/msm/dsi/dsi_ctrl.c b/msm/dsi/dsi_ctrl.c index 599e8a9f5e..241aa21f8c 100644 --- a/msm/dsi/dsi_ctrl.c +++ b/msm/dsi/dsi_ctrl.c @@ -847,8 +847,8 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, bit_rate = config->bit_clk_rate_hz_override * num_of_lanes; } else if (config->panel_mode == DSI_OP_CMD_MODE) { /* Calculate the bit rate needed to match dsi transfer time */ - bit_rate = mult_frac(min_dsi_clk_hz, frame_time_us, - dsi_transfer_time_us); + bit_rate = min_dsi_clk_hz * frame_time_us; + do_div(bit_rate, dsi_transfer_time_us); bit_rate = bit_rate * num_of_lanes; } else { h_period = DSI_H_TOTAL_DSC(timing); diff --git a/msm/dsi/dsi_panel.c b/msm/dsi/dsi_panel.c index e48deb214e..c0bfe10c61 100644 --- a/msm/dsi/dsi_panel.c +++ b/msm/dsi/dsi_panel.c @@ -2492,6 +2492,7 @@ static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode, u32 len, i; int rc = 0; struct dsi_display_mode_priv_info *priv_info; + u64 pixel_clk_khz; if (!mode || !mode->priv_info) return -EINVAL; @@ -2520,9 +2521,11 @@ static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode, * function dsi_panel_calc_dsi_transfer_time( ) * as we set it based on dsi clock or mdp transfer time. */ - mode->pixel_clk_khz = (DSI_H_TOTAL_DSC(&mode->timing) * + pixel_clk_khz = (DSI_H_TOTAL_DSC(&mode->timing) * DSI_V_TOTAL(&mode->timing) * - mode->timing.refresh_rate) / 1000; + mode->timing.refresh_rate); + do_div(pixel_clk_khz, 1000); + mode->pixel_clk_khz = pixel_clk_khz; } return rc; @@ -3570,7 +3573,8 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config, struct dsi_display_mode *mode, u32 frame_threshold_us) { u32 frame_time_us,nslices; - u64 min_bitclk_hz, total_active_pixels, bits_per_line, pclk_rate_hz; + u64 min_bitclk_hz, total_active_pixels, bits_per_line, pclk_rate_hz, + dsi_transfer_time_us, pixel_clk_khz; struct msm_display_dsc_info *dsc = mode->timing.dsc; struct dsi_mode_info *timing = &mode->timing; struct dsi_display_mode *display_mode; @@ -3605,15 +3609,18 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config, * timing->v_active)); /* calculate the actual bitclk needed to transfer the frame */ min_bitclk_hz = (total_active_pixels * (timing->refresh_rate) * - (config->bpp)) / (config->num_data_lanes); + (config->bpp)); + do_div(min_bitclk_hz, config->num_data_lanes); } timing->min_dsi_clk_hz = min_bitclk_hz; if (timing->clk_rate_hz) { /* adjust the transfer time proportionately for bit clk*/ - timing->dsi_transfer_time_us = mult_frac(frame_time_us, - min_bitclk_hz, timing->clk_rate_hz); + dsi_transfer_time_us = frame_time_us * min_bitclk_hz; + do_div(dsi_transfer_time_us, timing->clk_rate_hz); + timing->dsi_transfer_time_us = dsi_transfer_time_us; + } else if (mode->priv_info->mdp_transfer_time_us) { timing->dsi_transfer_time_us = mode->priv_info->mdp_transfer_time_us; @@ -3655,13 +3662,14 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config, } /* Calculate pclk_khz to update modeinfo */ - pclk_rate_hz = mult_frac(min_bitclk_hz, frame_time_us, - timing->dsi_transfer_time_us); + pclk_rate_hz = min_bitclk_hz * frame_time_us; + do_div(pclk_rate_hz, timing->dsi_transfer_time_us); - display_mode->pixel_clk_khz = mult_frac(pclk_rate_hz, - config->num_data_lanes, config->bpp); + pixel_clk_khz = pclk_rate_hz * config->num_data_lanes; + do_div(pixel_clk_khz, config->bpp); + display_mode->pixel_clk_khz = pixel_clk_khz; - do_div(display_mode->pixel_clk_khz, 1000); + display_mode->pixel_clk_khz = display_mode->pixel_clk_khz / 1000; } diff --git a/msm/dsi/dsi_phy_timing_v4_0.c b/msm/dsi/dsi_phy_timing_v4_0.c index 8e8927adc8..eb6a8f7c22 100644 --- a/msm/dsi/dsi_phy_timing_v4_0.c +++ b/msm/dsi/dsi_phy_timing_v4_0.c @@ -26,7 +26,7 @@ int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult) s64 rec_temp2, rec_temp3; rec_temp2 = rec_temp1; - rec_temp3 = roundup(div_s64(rec_temp2, 8), mult); + rec_temp3 = roundup64(div_s64(rec_temp2, 8), mult); return (div_s64(rec_temp3, mult) - 1); } @@ -37,7 +37,7 @@ int32_t dsi_phy_hw_v4_0_calc_clk_trail_rec_min(s64 temp_mul, rec_temp1 = temp_mul; rec_temp2 = div_s64(rec_temp1, 8); - rec_temp3 = roundup(rec_temp2, mult); + rec_temp3 = roundup64(rec_temp2, mult); return (div_s64(rec_temp3, mult) - 1); } @@ -53,7 +53,7 @@ int32_t dsi_phy_hw_v4_0_calc_hs_zero(s64 temp1, s64 mult) { s64 rec_temp2, rec_min; - rec_temp2 = roundup((temp1 / 8), mult); + rec_temp2 = roundup64((temp1 / 8), mult); rec_min = rec_temp2 - (1 * mult); return div_s64(rec_min, mult); } diff --git a/msm/msm_smmu.c b/msm/msm_smmu.c index d61f345022..8742b30417 100644 --- a/msm/msm_smmu.c +++ b/msm/msm_smmu.c @@ -451,7 +451,7 @@ static int msm_smmu_probe(struct platform_device *pdev) client->dev->dma_parms = devm_kzalloc(client->dev, sizeof(*client->dev->dma_parms), GFP_KERNEL); dma_set_max_seg_size(client->dev, DMA_BIT_MASK(32)); - dma_set_seg_boundary(client->dev, DMA_BIT_MASK(64)); + dma_set_seg_boundary(client->dev, (unsigned long)DMA_BIT_MASK(64)); iommu_set_fault_handler(client->domain, msm_smmu_fault_handler, (void *)client); diff --git a/msm/sde/sde_crtc.c b/msm/sde/sde_crtc.c index 2265a2abaa..e0c24b929a 100644 --- a/msm/sde/sde_crtc.c +++ b/msm/sde/sde_crtc.c @@ -276,7 +276,7 @@ static ssize_t measured_fps_show(struct device *device, { struct drm_crtc *crtc; struct sde_crtc *sde_crtc; - unsigned int fps_int, fps_decimal; + uint64_t fps_int, fps_decimal; u64 fps = 0, frame_count = 0; ktime_t current_time; int i = 0, current_time_index; @@ -353,7 +353,7 @@ static ssize_t measured_fps_show(struct device *device, } } - fps_int = (unsigned int) sde_crtc->fps_info.measured_fps; + fps_int = (uint64_t) sde_crtc->fps_info.measured_fps; fps_decimal = do_div(fps_int, 10); return scnprintf(buf, PAGE_SIZE, "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal, diff --git a/msm/sde_power_handle.h b/msm/sde_power_handle.h index 3505c2b0ed..2587c3734f 100644 --- a/msm/sde_power_handle.h +++ b/msm/sde_power_handle.h @@ -14,8 +14,8 @@ #define SDE_POWER_HANDLE_ENABLE_NRT_BUS_IB_QUOTA 0 #define SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0 -#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA 3000000000 -#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA 3000000000 +#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA 3000000000ULL +#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA 3000000000ULL #include #include diff --git a/pll/dsi_pll.h b/pll/dsi_pll.h index f944ad1001..35aa814941 100644 --- a/pll/dsi_pll.h +++ b/pll/dsi_pll.h @@ -23,8 +23,8 @@ struct lpfr_cfg { struct dsi_pll_vco_clk { struct clk_hw hw; unsigned long ref_clk_rate; - unsigned long min_rate; - unsigned long max_rate; + u64 min_rate; + u64 max_rate; u32 pll_en_seq_cnt; struct lpfr_cfg *lpfr_lut; u32 lpfr_lut_size; diff --git a/pll/dsi_pll_14nm_util.c b/pll/dsi_pll_14nm_util.c index 74f6eaf371..5cd7869cf7 100644 --- a/pll/dsi_pll_14nm_util.c +++ b/pll/dsi_pll_14nm_util.c @@ -1062,10 +1062,11 @@ long pll_vco_round_rate_14nm(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long rrate = rate; - u32 div; + u64 div; struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw); - div = vco->min_rate / rate; + div = vco->min_rate; + do_div(div, rate); if (div > 15) { /* rate < 86.67 Mhz */ pr_err("rate=%lu NOT supportted\n", rate); diff --git a/pll/dsi_pll_7nm.c b/pll/dsi_pll_7nm.c index 3cd11e7a8f..6eaa7f383b 100644 --- a/pll/dsi_pll_7nm.c +++ b/pll/dsi_pll_7nm.c @@ -576,11 +576,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, break; case MDSS_DSI_PLL_7NM_V4_1: default: - if (pll_freq <= 1000000000) + if (pll_freq <= 1000000000ULL) regs->pll_clock_inverters = 0xA0; - else if (pll_freq <= 2500000000) + else if (pll_freq <= 2500000000ULL) regs->pll_clock_inverters = 0x20; - else if (pll_freq <= 3020000000) + else if (pll_freq <= 3020000000ULL) regs->pll_clock_inverters = 0x00; else regs->pll_clock_inverters = 0x40; @@ -680,16 +680,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, break; case MDSS_DSI_PLL_7NM_V4_1: default: - if (vco_rate < 3100000000) + if (vco_rate < 3100000000ULL) MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01); else MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x03); - if (vco_rate < 1520000000) + if (vco_rate < 1520000000ULL) MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08); - else if (vco_rate < 2990000000) + else if (vco_rate < 2990000000ULL) MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01); else MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00); diff --git a/rotator/sde_rotator_smmu.c b/rotator/sde_rotator_smmu.c index 6e251541b0..5e323dabb4 100644 --- a/rotator/sde_rotator_smmu.c +++ b/rotator/sde_rotator_smmu.c @@ -617,7 +617,7 @@ int sde_smmu_probe(struct platform_device *pdev) sizeof(*dev->dma_parms), GFP_KERNEL); dma_set_max_seg_size(dev, DMA_BIT_MASK(32)); - dma_set_seg_boundary(dev, DMA_BIT_MASK(64)); + dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64)); iommu_set_fault_handler(sde_smmu->rot_domain, sde_smmu_fault_handler, (void *)sde_smmu);