diff --git a/msm/sde/sde_hw_ctl.c b/msm/sde/sde_hw_ctl.c
index 29d70201c6..d01572aa77 100644
--- a/msm/sde/sde_hw_ctl.c
+++ b/msm/sde/sde_hw_ctl.c
@@ -71,6 +71,8 @@
 
 #define UPDATE_ACTIVE(r, idx, en)  UPDATE_MASK((r), (idx), (en))
 
+#define DNSC_BLUR_IDX(i) (i + 16)
+
 /**
  * List of SSPP bits in CTL_FLUSH
  */
@@ -583,6 +585,17 @@ static inline int sde_hw_ctl_update_bitmask_v1(struct sde_hw_ctl *ctx,
 	return 0;
 }
 
+static inline void sde_hw_ctl_update_dnsc_blur_bitmask(struct sde_hw_ctl *ctx,
+		u32 blk_idx, bool enable)
+{
+	if (enable)
+		ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] |=
+					BIT(DNSC_BLUR_IDX(blk_idx) - DNSC_BLUR_0);
+	else
+		ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] &=
+					~BIT(DNSC_BLUR_IDX(blk_idx) - DNSC_BLUR_0);
+}
+
 static inline int sde_hw_ctl_update_pending_flush_v1(
 		struct sde_hw_ctl *ctx,
 		struct sde_ctl_flush_cfg *cfg)
@@ -1003,6 +1016,11 @@ static int sde_hw_ctl_intf_cfg_v1(struct sde_hw_ctl *ctx,
 			wb_active |= BIT(cfg->wb[i] - WB_0);
 	}
 
+	for (i = 0; i < cfg->dnsc_blur_count; i++) {
+		if (cfg->dnsc_blur[i])
+			wb_active |= BIT(DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0));
+	}
+
 	for (i = 0; i < cfg->merge_3d_count; i++) {
 		if (cfg->merge_3d[i])
 			merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
@@ -1059,6 +1077,13 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
 		}
 	}
 
+	for (i = 0; i < cfg->dnsc_blur_count; i++) {
+		if (cfg->dnsc_blur[i]) {
+			wb_active &= ~BIT(DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0));
+			wb_flush |= BIT(DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0));
+		}
+	}
+
 	if (merge_3d_idx) {
 		/* disable and flush merge3d_blk */
 		merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
@@ -1116,6 +1141,17 @@ static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
 		SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
 	}
 
+	if (cfg->dnsc_blur_count) {
+		wb_active = SDE_REG_READ(c, CTL_WB_ACTIVE);
+		for (i = 0; i < cfg->dnsc_blur_count; i++) {
+			if (cfg->dnsc_blur[i])
+				UPDATE_ACTIVE(wb_active,
+					DNSC_BLUR_IDX(cfg->dnsc_blur[i] - DNSC_BLUR_0),
+					enable);
+		}
+		SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
+	}
+
 	if (cfg->merge_3d_count) {
 		merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
 		for (i = 0; i < cfg->merge_3d_count; i++) {
@@ -1286,6 +1322,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
 		ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
 
 		ops->update_bitmask = sde_hw_ctl_update_bitmask_v1;
+		ops->update_dnsc_blur_bitmask = sde_hw_ctl_update_dnsc_blur_bitmask;
 		ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;
 
 		ops->reset_post_disable = sde_hw_ctl_reset_post_disable;
diff --git a/msm/sde/sde_hw_ctl.h b/msm/sde/sde_hw_ctl.h
index 45b6749566..b842e80c3f 100644
--- a/msm/sde/sde_hw_ctl.h
+++ b/msm/sde/sde_hw_ctl.h
@@ -109,6 +109,8 @@ struct sde_hw_intf_cfg {
  * @dsc:                      Id of active dsc blocks
  * @vdc_count:                No. of active vdc blocks
  * @vdc:                      Id of active vdc blocks
+ * @dnsc_blur_count:          No. of active downscale blur blocks
+ * @dnsc_blur:                Id of active downscale blur blocks
  */
 struct sde_hw_intf_cfg_v1 {
 	uint32_t intf_count;
@@ -133,6 +135,9 @@ struct sde_hw_intf_cfg_v1 {
 
 	uint32_t vdc_count;
 	enum sde_vdc vdc[MAX_VDC_PER_CTL_V1];
+
+	uint32_t dnsc_blur_count;
+	enum sde_dnsc_blur dnsc_blur[MAX_VDC_PER_CTL_V1];
 };
 
 /**
@@ -379,6 +384,14 @@ struct sde_hw_ctl_ops {
 	int (*update_bitmask)(struct sde_hw_ctl *ctx,
 			enum ctl_hw_flush_type type, u32 blk_idx, bool enable);
 
+	/**
+	 * update_dnsc_blur_bitmask: updates dnsc_blur flush mask
+	 * @type              : blk type to flush
+	 * @blk_idx           : blk idx
+	 * @enable            : true to enable, 0 to disable
+	 */
+	void (*update_dnsc_blur_bitmask)(struct sde_hw_ctl *ctx, u32 blk_idx, bool enable);
+
 	/**
 	 * get interfaces for the active CTL .
 	 * @ctx		: ctl path ctx pointer