msm: eva: Add GCC reg mapping

For better SMMU fault debugging in future.

Change-Id: Iead03f9d701fc53690fb0b6864562e65f2cfc15f
Signed-off-by: George Shen <[email protected]>

msm/eva/cvp_hfi.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <asm/memory.h>
@@ -3256,6 +3256,16 @@ static int __init_regs_and_interrupts(struct iris_hfi_device *device,
 		goto error_irq_fail;
 	}
 
+	if (res->gcc_reg_base) {
+		hal->gcc_reg_base = devm_ioremap(&res->pdev->dev,
+				res->gcc_reg_base, res->gcc_reg_size);
+		hal->gcc_reg_size = res->gcc_reg_size;
+		if (!hal->gcc_reg_base)
+			dprintk(CVP_ERR,
+				"could not map gcc reg addr %pa of size %d\n",
+				&res->gcc_reg_base, res->gcc_reg_size);
+	}
+
 	device->cvp_hal_data = hal;
 	rc = request_irq(res->irq, iris_hfi_isr, IRQF_TRIGGER_HIGH,
 			"msm_cvp", device);
@@ -4199,27 +4209,7 @@ static void power_off_iris2(struct iris_hfi_device *device)
 			sbm_ln0_low, main_sbm_ln0_low, main_sbm_ln1_high);
 	}
 
-	/* HPG 6.1.2 Step 3, debug bridge to low power */
-	__write_register(device,
-		CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
-
-	reg_status = 0;
-	count = 0;
-	while ((reg_status != 0x7) && count < max_count) {
-		lpi_status = __read_register(device,
-			CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
-		reg_status = lpi_status & 0x7;
-		/* Wait for debug bridge lpi status to be set */
-		usleep_range(50, 100);
-		count++;
-	}
-	dprintk(CVP_PWR,
-		"DBLP Set : lpi_status %d reg_status %d (count %d)\n",
-		lpi_status, reg_status, count);
-	if (count == max_count) {
-		dprintk(CVP_WARN,
-			"DBLP Set: status %x %x\n", reg_status, lpi_status);
-	}
+	/* HPG 6.1.2 Step 3, debug bridge to low power BYPASSED */
 
 	/* HPG 6.1.2 Step 4, debug bridge to lpi release */
 	__write_register(device,

msm/eva/msm_cvp_res_parse.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/iommu.h>
@@ -134,6 +134,26 @@ static int msm_cvp_load_ipcc_regs(struct msm_cvp_platform_resources *res)
 	return ret;
 }
 
+static int msm_cvp_load_gcc_regs(struct msm_cvp_platform_resources *res)
+{
+	int ret = 0;
+	unsigned int reg_config[2];
+	struct platform_device *pdev = res->pdev;
+
+	ret = of_property_read_u32_array(pdev->dev.of_node, "qcom,gcc-reg",
+				reg_config, 2);
+	if (ret) {
+		dprintk(CVP_WARN, "No gcc reg configured: %d\n", ret);
+		return ret;
+	}
+
+	res->gcc_reg_base = reg_config[0];
+	res->gcc_reg_size = reg_config[1];
+
+	return ret;
+}
+
+
 static int msm_cvp_load_reg_table(struct msm_cvp_platform_resources *res)
 {
 	struct reg_set *reg_set;
@@ -809,6 +829,8 @@ int cvp_read_platform_resources_from_dt(
 	if (rc)
 		dprintk(CVP_ERR, "Failed to load IPCC regs: %d\n", rc);
 
+	rc = msm_cvp_load_gcc_regs(res);
+
 	rc = msm_cvp_load_regulator_table(res);
 	if (rc) {
 		dprintk(CVP_ERR, "Failed to load list of regulators %d\n", rc);

msm/eva/msm_cvp_resources.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef __MSM_CVP_RESOURCES_H__
@@ -137,8 +137,10 @@ struct msm_cvp_platform_resources {
 	phys_addr_t firmware_base;
 	phys_addr_t register_base;
 	phys_addr_t ipcc_reg_base;
+	phys_addr_t gcc_reg_base;
 	uint32_t register_size;
 	uint32_t ipcc_reg_size;
+	uint32_t gcc_reg_size;
 	uint32_t irq;
 	uint32_t sku_version;
 	struct allowed_clock_rates_table *allowed_clks_tbl;