samsung-sm8650/android_kernel_samsung_sm8650-modules
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Merge "disp: msm: typecast variables as long long for 64 bit operations"

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This commit is contained in:
qctecmdr
2021-05-02 18:40:35 -07:00
committed by Gerrit - the friendly Code Review server
parent 6614e279eb 2ec9452162
commit bf67f9d761
6 changed files with 18 additions and 17 deletions
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12
msm/dsi/dsi_pll_5nm.c
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@@ -271,11 +271,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_5nm *pll,
switch (rsc->pll_revision) { switch (rsc->pll_revision) {
case DSI_PLL_5NM: case DSI_PLL_5NM:
default: default:
if (pll_freq <= 1000000000) if (pll_freq <= 1000000000ULL)
regs->pll_clock_inverters = 0xA0; regs->pll_clock_inverters = 0xA0;
else if (pll_freq <= 2500000000) else if (pll_freq <= 2500000000ULL)
regs->pll_clock_inverters = 0x20; regs->pll_clock_inverters = 0x20;
else if (pll_freq <= 3500000000) else if (pll_freq <= 3500000000ULL)
regs->pll_clock_inverters = 0x00; regs->pll_clock_inverters = 0x00;
else else
regs->pll_clock_inverters = 0x40; regs->pll_clock_inverters = 0x40;
@@ -370,16 +370,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_5nm *pll,
switch (rsc->pll_revision) { switch (rsc->pll_revision) {
case DSI_PLL_5NM: case DSI_PLL_5NM:
default: default:
if (vco_rate < 3100000000) if (vco_rate < 3100000000ULL)
DSI_PLL_REG_W(pll_base, DSI_PLL_REG_W(pll_base,
PLL_ANALOG_CONTROLS_FIVE_1, 0x01); PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
else else
DSI_PLL_REG_W(pll_base, DSI_PLL_REG_W(pll_base,
PLL_ANALOG_CONTROLS_FIVE_1, 0x03); PLL_ANALOG_CONTROLS_FIVE_1, 0x03);
if (vco_rate < 1520000000) if (vco_rate < 1520000000ULL)
DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08); DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);
else if (vco_rate < 2990000000) else if (vco_rate < 2990000000ULL)
DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00); DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
else else
DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01); DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);

7
msm/sde/sde_hw_color_proc_v4.c
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@@ -410,10 +410,9 @@ void sde_demura_backlight_cfg(struct sde_hw_dspp *ctx, u64 val)
} }
demura_base = ctx->cap->sblk->demura.base; demura_base = ctx->cap->sblk->demura.base;
backlight = (val & REG_MASK(11)); backlight = (val & REG_MASK_ULL(11));
backlight |= ((val & REG_MASK_SHIFT(11, 32)) >> 16); backlight |= ((val & REG_MASK_SHIFT_ULL(11, 32)) >> 16);
SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->demura.base + 0x8, SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->demura.base + 0x8, backlight);
backlight);
} }
void sde_setup_fp16_cscv1(struct sde_hw_pipe *ctx, void sde_setup_fp16_cscv1(struct sde_hw_pipe *ctx,

3
msm/sde/sde_hw_reg_dma_v1.c
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@@ -880,7 +880,8 @@ static int check_support_v1(enum sde_reg_dma_features feature,
if (!is_supported) if (!is_supported)
return -EINVAL; return -EINVAL;
if (feature >= REG_DMA_FEATURES_MAX || blk >= BIT(REG_DMA_BLK_MAX)) { if (feature >= REG_DMA_FEATURES_MAX
|| blk >= BIT_ULL(REG_DMA_BLK_MAX)) {
*is_supported = false; *is_supported = false;
return ret; return ret;
} }

7
msm/sde/sde_hw_reg_dma_v1_color_proc.c
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@@ -12,6 +12,7 @@
#include "sde_hwio.h" #include "sde_hwio.h"
#include "sde_hw_lm.h" #include "sde_hw_lm.h"
#include "sde_dbg.h" #include "sde_dbg.h"
#include "sde_hw_util.h"
/* Reserve space of 128 words for LUT dma payload set-up */ /* Reserve space of 128 words for LUT dma payload set-up */
#define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128) #define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
@@ -82,8 +83,6 @@
#define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \ #define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \
REG_DMA_HEADERS_BUFFER_SZ) REG_DMA_HEADERS_BUFFER_SZ)
#define REG_MASK(n) ((BIT(n)) - 1)
#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
#define APPLY_MASK_AND_SHIFT(x, n, shift) ((x & (REG_MASK(n))) << (shift)) #define APPLY_MASK_AND_SHIFT(x, n, shift) ((x & (REG_MASK(n))) << (shift))
#define REG_DMA_VIG_GAMUT_OP_MASK 0x300 #define REG_DMA_VIG_GAMUT_OP_MASK 0x300
#define REG_DMA_VIG_IGC_OP_MASK 0x1001F #define REG_DMA_VIG_IGC_OP_MASK 0x1001F
@@ -4919,8 +4918,8 @@ static int __reg_dmav1_setup_demurav1_cfg0_c_params(
} }
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
temp[i * 2] = p[i] & REG_MASK(32); temp[i * 2] = p[i] & REG_MASK_ULL(32);
temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT(10, 32)) >> 32; temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT_ULL(10, 32)) >> 32;
DRM_DEBUG_DRIVER("0x6c: index %d value %x\n", DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",
i * 2, temp[i * 2]); i * 2, temp[i * 2]);
DRM_DEBUG_DRIVER("0x6c: index %d value %x\n", DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",

4
msm/sde/sde_hw_util.h
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@@ -12,7 +12,9 @@
#include "sde_hw_catalog.h" #include "sde_hw_catalog.h"
#define REG_MASK(n) ((BIT(n)) - 1) #define REG_MASK(n) ((BIT(n)) - 1)
#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift)) #define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
#define REG_MASK_ULL(n) ((BIT_ULL(n)) - 1)
#define REG_MASK_SHIFT_ULL(n, shift) ((REG_MASK_ULL(n)) << (shift))
#define LP_DDR4_TYPE 0x7 #define LP_DDR4_TYPE 0x7
struct sde_format_extended; struct sde_format_extended;

2
msm/sde_vdc_helper.c
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@@ -550,7 +550,7 @@ static int sde_vdc_populate_core_params(struct msm_display_vdc_info *vdc_info,
temp = temp << 16; temp = temp << 16;
vdc_info->ramp_bits = temp; vdc_info->ramp_bits = temp;
temp = vdc_info->ramp_bits / vdc_info->ramp_blocks; temp = div_u64(vdc_info->ramp_bits, (vdc_info->ramp_blocks) ? vdc_info->ramp_blocks : 1);
vdc_info->rc_fullness_offset_slope = temp; vdc_info->rc_fullness_offset_slope = temp;
temp = (2 * SSM_MAX_SE_SIZE) - 2; temp = (2 * SSM_MAX_SE_SIZE) - 2;