Merge "disp: msm: typecast variables as long long for 64 bit operations"
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@@ -271,11 +271,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_5nm *pll,
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switch (rsc->pll_revision) {
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case DSI_PLL_5NM:
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default:
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if (pll_freq <= 1000000000)
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if (pll_freq <= 1000000000ULL)
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regs->pll_clock_inverters = 0xA0;
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else if (pll_freq <= 2500000000)
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else if (pll_freq <= 2500000000ULL)
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regs->pll_clock_inverters = 0x20;
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else if (pll_freq <= 3500000000)
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else if (pll_freq <= 3500000000ULL)
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regs->pll_clock_inverters = 0x00;
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else
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regs->pll_clock_inverters = 0x40;
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@@ -370,16 +370,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_5nm *pll,
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switch (rsc->pll_revision) {
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case DSI_PLL_5NM:
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default:
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if (vco_rate < 3100000000)
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if (vco_rate < 3100000000ULL)
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DSI_PLL_REG_W(pll_base,
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PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
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else
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DSI_PLL_REG_W(pll_base,
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PLL_ANALOG_CONTROLS_FIVE_1, 0x03);
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if (vco_rate < 1520000000)
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if (vco_rate < 1520000000ULL)
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DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);
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else if (vco_rate < 2990000000)
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else if (vco_rate < 2990000000ULL)
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DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
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else
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DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);
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