qcacmn: Add stats for new TQM release reason on BE

Add Tx completion stats for TQM release reason added
for BE

Change-Id: I7d28cbfacd1378982c5cf9a3f2cf3cffa070ee87
This commit is contained in:
Chaithanya Garrepalli
2022-02-17 17:23:11 +05:30
کامیت شده توسط Madan Koyyalamudi
والد 3901980153
کامیت be02a2d44f
6فایلهای تغییر یافته به همراه215 افزوده شده و 93 حذف شده

مشاهده پرونده

@@ -3899,7 +3899,6 @@ dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
{
struct dp_pdev *pdev = txrx_peer->vdev->pdev;
struct dp_soc *soc = NULL;
uint8_t tid = ts->tid;
uint32_t length;
struct cdp_tid_tx_stats *tid_stats;
@@ -3911,7 +3910,6 @@ dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
tid = CDP_MAX_DATA_TIDS - 1;
tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
soc = pdev->soc;
if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
dp_err("Release source is not from TQM");
@@ -3923,68 +3921,83 @@ dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
if (qdf_unlikely(pdev->delay_stats_flag))
dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.age_out, 1,
(ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
DP_PEER_PER_PKT_STATS_INCC_PKT(txrx_peer, tx.dropped.fw_rem, 1, length,
(ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_rem_notx, 1,
(ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_rem_tx, 1,
(ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_reason1, 1,
(ts->status == HAL_TX_TQM_RR_FW_REASON1));
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_reason2, 1,
(ts->status == HAL_TX_TQM_RR_FW_REASON2));
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.dropped.fw_reason3, 1,
(ts->status == HAL_TX_TQM_RR_FW_REASON3));
/*
* tx_failed is ideally supposed to be updated from HTT ppdu completion
* stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
* are no completions for failed cases. Hence updating tx_failed from
* data path. Please note that if tx_failed is fixed to be from ppdu,
* then this has to be removed
*/
txrx_peer->tx_failed =
txrx_peer->stats.per_pkt_stats.tx.dropped.fw_rem.num +
txrx_peer->stats.per_pkt_stats.tx.dropped.fw_rem_notx +
txrx_peer->stats.per_pkt_stats.tx.dropped.fw_rem_tx +
txrx_peer->stats.per_pkt_stats.tx.dropped.age_out +
txrx_peer->stats.per_pkt_stats.tx.dropped.fw_reason1 +
txrx_peer->stats.per_pkt_stats.tx.dropped.fw_reason2 +
txrx_peer->stats.per_pkt_stats.tx.dropped.fw_reason3;
if (ts->status < CDP_MAX_TX_TQM_STATUS) {
tid_stats->tqm_status_cnt[ts->status]++;
}
if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
ts->transmit_cnt > DP_RETRY_COUNT);
dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
ts->transmit_cnt > 1);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
1, ts->transmit_cnt > 2);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
ts->msdu_part_of_amsdu);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
!ts->msdu_part_of_amsdu);
txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
qdf_system_ticks();
dp_tx_update_peer_extd_stats(ts, txrx_peer);
return;
}
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
ts->transmit_cnt > 1);
/*
* tx_failed is ideally supposed to be updated from HTT ppdu
* completion stats. But in IPQ807X/IPQ6018 chipsets owing to
* hw limitation there are no completions for failed cases.
* Hence updating tx_failed from data path. Please note that
* if tx_failed is fixed to be from ppdu, then this has to be
* removed
*/
DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count, 1,
ts->transmit_cnt > 2);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
ts->transmit_cnt > DP_RETRY_COUNT);
dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
ts->msdu_part_of_amsdu);
DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
!ts->msdu_part_of_amsdu);
txrx_peer->stats.per_pkt_stats.tx.last_tx_ts = qdf_system_ticks();
dp_tx_update_peer_extd_stats(ts, txrx_peer);
if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
} else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
length);
} else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
} else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
} else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
} else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
} else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
} else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer,
tx.dropped.fw_rem_queue_disable, 1);
} else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer,
tx.dropped.fw_rem_no_match, 1);
} else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer,
tx.dropped.drop_threshold, 1);
} else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer,
tx.dropped.drop_link_desc_na, 1);
} else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer,
tx.dropped.invalid_drop, 1);
} else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
DP_PEER_PER_PKT_STATS_INC(txrx_peer,
tx.dropped.mcast_vdev_drop, 1);
} else {
DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
}
}
#ifdef QCA_LL_TX_FLOW_CONTROL_V2