wlan_platform: Update CNSS family drivers

Update CNSS family drivers from msm-5.10 kernel as of commit
db1b2399e273 (Merge "cnss2: Increase power on retry delay")
to WLAN platform project. Also add proper copyright markings
for some files.

Change-Id: I03a10b929f5460f80a9b1f258df58e0c1a593598

cnss2/main.c

@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #include <linux/delay.h>
 #include <linux/jiffies.h>
@@ -27,12 +30,11 @@
 #define CNSS_DUMP_NAME			"CNSS_WLAN"
 #define CNSS_DUMP_DESC_SIZE		0x1000
 #define CNSS_DUMP_SEG_VER		0x1
-#define RECOVERY_DELAY_MS		100
 #define FILE_SYSTEM_READY		1
 #define FW_READY_TIMEOUT		20000
 #define FW_ASSERT_TIMEOUT		5000
 #define CNSS_EVENT_PENDING		2989
-#define COLD_BOOT_CAL_SHUTDOWN_DELAY_MS	50
+#define POWER_RESET_MIN_DELAY_MS	100
 
 #define CNSS_QUIRKS_DEFAULT		0
 #ifdef CONFIG_CNSS_EMULATION
@@ -857,7 +859,10 @@ unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
 		 */
 		return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
 	case CNSS_TIMEOUT_CALIBRATION:
-		return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT);
+		/* Similar to mission mode, in CBC if FW init fails
+		 * fw recovery is tried. Thus return 2x the CBC timeout.
+		 */
+		return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
 	case CNSS_TIMEOUT_WLAN_WATCHDOG:
 		return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
 	case CNSS_TIMEOUT_RDDM:
@@ -1316,7 +1321,7 @@ static void cnss_recovery_work_handler(struct work_struct *work)
 
 	cnss_bus_dev_shutdown(plat_priv);
 	cnss_bus_dev_ramdump(plat_priv);
-	msleep(RECOVERY_DELAY_MS);
+	msleep(POWER_RESET_MIN_DELAY_MS);
 
 	ret = cnss_bus_dev_powerup(plat_priv);
 	if (ret)
@@ -1756,7 +1761,7 @@ static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
 	cnss_bus_free_qdss_mem(plat_priv);
 	cnss_release_antenna_sharing(plat_priv);
 	cnss_bus_dev_shutdown(plat_priv);
-	msleep(COLD_BOOT_CAL_SHUTDOWN_DELAY_MS);
+	msleep(POWER_RESET_MIN_DELAY_MS);
 	complete(&plat_priv->cal_complete);
 	clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
 	set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
@@ -3408,6 +3413,10 @@ static int cnss_remove(struct platform_device *plat_dev)
 	cnss_unregister_bus_scale(plat_priv);
 	cnss_unregister_esoc(plat_priv);
 	cnss_put_resources(plat_priv);
+
+	if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
+		mbox_free_channel(plat_priv->mbox_chan);
+
 	platform_set_drvdata(plat_dev, NULL);
 	plat_env = NULL;
 

cnss2/main.h

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #ifndef _CNSS_MAIN_H
 #define _CNSS_MAIN_H
@@ -53,7 +56,7 @@
 #define MAX_FIRMWARE_NAME_LEN		40
 #define FW_V2_NUMBER                    2
 #define POWER_ON_RETRY_MAX_TIMES        3
-#define POWER_ON_RETRY_DELAY_MS         200
+#define POWER_ON_RETRY_DELAY_MS         500
 
 #define CNSS_EVENT_SYNC   BIT(0)
 #define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)

cnss2/pci.c

@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #include <linux/cma.h>
 #include <linux/io.h>
@@ -220,6 +223,7 @@ static const struct mhi_controller_config cnss_mhi_config = {
 	.ch_cfg = cnss_mhi_channels,
 	.num_events = ARRAY_SIZE(cnss_mhi_events),
 	.event_cfg = cnss_mhi_events,
+	.m2_no_db = true,
 };
 
 static struct cnss_pci_reg ce_src[] = {
@@ -1647,12 +1651,13 @@ EXPORT_SYMBOL(cnss_pci_unlock_reg_window);
  */
 static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
 {
-	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
 	u32 mem_addr, val, pbl_log_max_size, sbl_log_max_size;
-	u32 pbl_log_sram_start, sbl_log_def_start, sbl_log_def_end;
+	u32 pbl_log_sram_start;
 	u32 pbl_stage, sbl_log_start, sbl_log_size;
 	u32 pbl_wlan_boot_cfg, pbl_bootstrap_status;
 	u32 pbl_bootstrap_status_reg = PBL_BOOTSTRAP_STATUS;
+	u32 sbl_log_def_start = SRAM_START;
+	u32 sbl_log_def_end = SRAM_END;
 	int i;
 
 	switch (pci_priv->device_id) {
@@ -1660,28 +1665,17 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
 		pbl_log_sram_start = QCA6390_DEBUG_PBL_LOG_SRAM_START;
 		pbl_log_max_size = QCA6390_DEBUG_PBL_LOG_SRAM_MAX_SIZE;
 		sbl_log_max_size = QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE;
-		sbl_log_def_start = QCA6390_V2_SBL_DATA_START;
-		sbl_log_def_end = QCA6390_V2_SBL_DATA_END;
 		break;
 	case QCA6490_DEVICE_ID:
 		pbl_log_sram_start = QCA6490_DEBUG_PBL_LOG_SRAM_START;
 		pbl_log_max_size = QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE;
 		sbl_log_max_size = QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE;
-		if (plat_priv->device_version.major_version == FW_V2_NUMBER) {
-			sbl_log_def_start = QCA6490_V2_SBL_DATA_START;
-			sbl_log_def_end = QCA6490_V2_SBL_DATA_END;
-		} else {
-			sbl_log_def_start = QCA6490_V1_SBL_DATA_START;
-			sbl_log_def_end = QCA6490_V1_SBL_DATA_END;
-		}
 		break;
 	case WCN7850_DEVICE_ID:
 		pbl_bootstrap_status_reg = WCN7850_PBL_BOOTSTRAP_STATUS;
 		pbl_log_sram_start = WCN7850_DEBUG_PBL_LOG_SRAM_START;
 		pbl_log_max_size = WCN7850_DEBUG_PBL_LOG_SRAM_MAX_SIZE;
 		sbl_log_max_size = WCN7850_DEBUG_SBL_LOG_SRAM_MAX_SIZE;
-		sbl_log_def_start = WCN7850_SBL_DATA_START;
-		sbl_log_def_end = WCN7850_SBL_DATA_END;
 	default:
 		return;
 	}
@@ -1945,6 +1939,12 @@ retry_mhi_suspend:
 		break;
 	case CNSS_MHI_TRIGGER_RDDM:
 		ret = mhi_force_rddm_mode(pci_priv->mhi_ctrl);
+		if (ret) {
+			cnss_pr_err("Failed to trigger RDDM, err = %d\n", ret);
+
+			cnss_pr_dbg("Sending host reset req\n");
+			ret = mhi_force_reset(pci_priv->mhi_ctrl);
+		}
 		break;
 	case CNSS_MHI_RDDM_DONE:
 		break;
@@ -2689,7 +2689,7 @@ static int cnss_qca6290_powerup(struct cnss_pci_data *pci_priv)
 	int ret = 0;
 	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
 	unsigned int timeout;
-	int retry = 0;
+	int retry = 0, bt_en_gpio = plat_priv->pinctrl_info.bt_en_gpio;
 
 	if (plat_priv->ramdump_info_v2.dump_data_valid) {
 		cnss_pci_clear_dump_info(pci_priv);
@@ -2721,6 +2721,15 @@ retry:
 		}
 		if (ret == -EAGAIN && retry++ < POWER_ON_RETRY_MAX_TIMES) {
 			cnss_power_off_device(plat_priv);
+			/* Force toggle BT_EN GPIO low */
+			if (retry == POWER_ON_RETRY_MAX_TIMES) {
+				cnss_pr_dbg("Retry #%d. Set BT_EN GPIO(%u) low\n",
+					    retry, bt_en_gpio);
+				if (bt_en_gpio >= 0)
+					gpio_direction_output(bt_en_gpio, 0);
+				cnss_pr_dbg("BT_EN GPIO val: %d\n",
+					    gpio_get_value(bt_en_gpio));
+			}
 			cnss_pr_dbg("Retry to resume PCI link #%d\n", retry);
 			msleep(POWER_ON_RETRY_DELAY_MS * retry);
 			goto retry;
@@ -3014,7 +3023,10 @@ static void cnss_wlan_reg_driver_work(struct work_struct *work)
 	if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
 		goto reg_driver;
 	} else {
-		cnss_pr_err("Calibration still not done\n");
+		cnss_pr_err("Timeout waiting for calibration to complete\n");
+		del_timer(&plat_priv->fw_boot_timer);
+		if (!test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state))
+			CNSS_ASSERT(0);
 		cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
 		if (!cal_info)
 			return;
@@ -3022,8 +3034,6 @@ static void cnss_wlan_reg_driver_work(struct work_struct *work)
 		cnss_driver_event_post(plat_priv,
 				       CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
 				       0, cal_info);
-		/* Temporarily return for bringup. CBC will not be triggered */
-		return;
 	}
 reg_driver:
 	if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
@@ -5188,6 +5198,8 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
 	rddm_image = pci_priv->mhi_ctrl->rddm_image;
 	dump_data->nentries = 0;
 
+	cnss_mhi_dump_sfr(pci_priv);
+
 	if (!dump_seg) {
 		cnss_pr_warn("FW image dump collection not setup");
 		goto skip_dump;
@@ -5219,8 +5231,6 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
 
 	dump_data->nentries += rddm_image->entries;
 
-	cnss_mhi_dump_sfr(pci_priv);
-
 	cnss_pr_dbg("Collect remote heap dump segment\n");
 
 	for (i = 0, j = 0; i < plat_priv->fw_mem_seg_len; i++) {
@@ -5761,6 +5771,8 @@ static irqreturn_t cnss_pci_wake_handler(int irq, void *data)
 {
 	struct cnss_pci_data *pci_priv = data;
 	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
+	enum rpm_status status;
+	struct device *dev;
 
 	pci_priv->wake_counter++;
 	cnss_pr_dbg("WLAN PCI wake IRQ (%u) is asserted #%u\n",
@@ -5776,8 +5788,12 @@ static irqreturn_t cnss_pci_wake_handler(int irq, void *data)
 	 */
 	pm_system_wakeup();
 
-	if (cnss_pci_get_monitor_wake_intr(pci_priv) &&
+	dev = &pci_priv->pci_dev->dev;
-	    cnss_pci_get_auto_suspended(pci_priv)) {
+	status = dev->power.runtime_status;
+
+	if ((cnss_pci_get_monitor_wake_intr(pci_priv) &&
+	     cnss_pci_get_auto_suspended(pci_priv)) ||
+	    (status == RPM_SUSPENDING || status == RPM_SUSPENDED)) {
 		cnss_pci_set_monitor_wake_intr(pci_priv, false);
 		cnss_pci_pm_request_resume(pci_priv);
 	}

cnss2/power.c

@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #include <linux/clk.h>
 #include <linux/delay.h>
@@ -1087,12 +1090,6 @@ int cnss_aop_mbox_init(struct cnss_plat_data *plat_priv)
 	mbox->knows_txdone = false;
 
 	plat_priv->mbox_chan = NULL;
-	chan = mbox_request_channel(mbox, 0);
-	if (IS_ERR(chan)) {
-		cnss_pr_err("Failed to get mbox channel\n");
-		return PTR_ERR(chan);
-	}
-	plat_priv->mbox_chan = chan;
 
 	ret = of_property_read_string(plat_priv->plat_dev->dev.of_node,
 				      "qcom,vreg_ol_cpr",
@@ -1106,7 +1103,18 @@ int cnss_aop_mbox_init(struct cnss_plat_data *plat_priv)
 	if (ret)
 		cnss_pr_dbg("Volt regulator for Int Power Amp not configured\n");
 
+	if (!plat_priv->vreg_ol_cpr && !plat_priv->vreg_ipa)
+		return 0;
+
+	chan = mbox_request_channel(mbox, 0);
+	if (IS_ERR(chan)) {
+		cnss_pr_err("Failed to get mbox channel\n");
+		return PTR_ERR(chan);
+	}
+
+	plat_priv->mbox_chan = chan;
 	cnss_pr_dbg("Mbox channel initialized\n");
+
 	return 0;
 }
 

cnss2/reg.h

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #ifndef _CNSS_REG_H
 #define _CNSS_REG_H
@@ -75,22 +78,14 @@
 
 #define QCA6390_DEBUG_PBL_LOG_SRAM_START	0x01403D58
 #define QCA6390_DEBUG_PBL_LOG_SRAM_MAX_SIZE	80
-#define QCA6390_V2_SBL_DATA_START		0x016C8580
-#define QCA6390_V2_SBL_DATA_END			(0x016C8580 + 0x00011000)
 #define QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE	44
 
 #define QCA6490_DEBUG_PBL_LOG_SRAM_START	0x01403DA0
 #define QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE	40
-#define QCA6490_V1_SBL_DATA_START		0x0143B000
-#define QCA6490_V1_SBL_DATA_END			(0x0143B000 + 0x00011000)
-#define QCA6490_V2_SBL_DATA_START		0x01435000
-#define QCA6490_V2_SBL_DATA_END			(0x01435000 + 0x00011000)
 #define QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE	48
 
 #define WCN7850_DEBUG_PBL_LOG_SRAM_START	0x01403D98
 #define WCN7850_DEBUG_PBL_LOG_SRAM_MAX_SIZE	40
-#define WCN7850_SBL_DATA_START			0x01790000
-#define WCN7850_SBL_DATA_END			(0x01790000 + 0x00011000)
 #define WCN7850_DEBUG_SBL_LOG_SRAM_MAX_SIZE	48
 #define WCN7850_PBL_BOOTSTRAP_STATUS		0x01A10008
 
@@ -99,6 +94,8 @@
 #define PCIE_BHI_ERRDBG3_REG			0x01E0E23C
 #define PBL_WLAN_BOOT_CFG			0x01E22B34
 #define PBL_BOOTSTRAP_STATUS			0x01910008
+#define SRAM_START				0x01400000
+#define SRAM_END				0x01800000
 
 #define QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG 0x01E04234
 #define QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG_VAL 0xDEAD1234

cnss_utils/cnss_plat_ipc_qmi.c

@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2021, The Linux Foundation. All rights reserved. */
+/*
-
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/qrtr.h>
@@ -737,7 +739,7 @@ static struct qmi_msg_handler cnss_plat_ipc_qmi_req_handlers[] = {
 		.msg_id = CNSS_PLAT_IPC_QMI_REG_CLIENT_REQ_V01,
 		.ei = cnss_plat_ipc_qmi_reg_client_req_msg_v01_ei,
 		.decoded_size =
-			CNSS_PLAT_IPC_QMI_REG_CLIENT_REQ_MSG_V01_MAX_MSG_LEN,
+		sizeof(struct cnss_plat_ipc_qmi_reg_client_req_msg_v01),
 		.fn = cnss_plat_ipc_qmi_reg_client_req_handler,
 	},
 	{
@@ -745,7 +747,7 @@ static struct qmi_msg_handler cnss_plat_ipc_qmi_req_handlers[] = {
 		.msg_id = CNSS_PLAT_IPC_QMI_INIT_SETUP_REQ_V01,
 		.ei = cnss_plat_ipc_qmi_init_setup_req_msg_v01_ei,
 		.decoded_size =
-			CNSS_PLAT_IPC_QMI_INIT_SETUP_REQ_MSG_V01_MAX_MSG_LEN,
+		sizeof(struct cnss_plat_ipc_qmi_init_setup_req_msg_v01),
 		.fn = cnss_plat_ipc_qmi_init_setup_req_handler,
 	},
 	{
@@ -753,7 +755,7 @@ static struct qmi_msg_handler cnss_plat_ipc_qmi_req_handlers[] = {
 		.msg_id = CNSS_PLAT_IPC_QMI_FILE_DOWNLOAD_REQ_V01,
 		.ei = cnss_plat_ipc_qmi_file_download_req_msg_v01_ei,
 		.decoded_size =
-			CNSS_PLAT_IPC_QMI_FILE_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
+		sizeof(struct cnss_plat_ipc_qmi_file_download_req_msg_v01),
 		.fn = cnss_plat_ipc_qmi_file_download_req_handler,
 	},
 	{
@@ -761,7 +763,7 @@ static struct qmi_msg_handler cnss_plat_ipc_qmi_req_handlers[] = {
 		.msg_id = CNSS_PLAT_IPC_QMI_FILE_UPLOAD_REQ_V01,
 		.ei = cnss_plat_ipc_qmi_file_upload_req_msg_v01_ei,
 		.decoded_size =
-			CNSS_PLAT_IPC_QMI_FILE_UPLOAD_REQ_MSG_V01_MAX_MSG_LEN,
+		sizeof(struct cnss_plat_ipc_qmi_file_upload_req_msg_v01),
 		.fn = cnss_plat_ipc_qmi_file_upload_req_handler,
 	},
 	{}