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@@ -9455,16 +9455,35 @@ static inline void hdd_pm_qos_update_request(struct hdd_context *hdd_ctx,
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int cpu;
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unsigned int latency;
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- cpumask_copy(&hdd_ctx->qos_cpu_mask, pm_qos_cpu_mask);
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+ qdf_cpumask_copy(&hdd_ctx->qos_cpu_mask, pm_qos_cpu_mask);
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- if (cpumask_empty(pm_qos_cpu_mask))
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+ if (qdf_cpumask_empty(pm_qos_cpu_mask)) {
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latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
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- else
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+ qdf_for_each_possible_cpu(cpu) {
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+ dev_pm_qos_update_request(
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+ &hdd_ctx->pm_qos_req[cpu],
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+ latency);
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+ }
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+ hdd_debug("Empty mask %*pb: Set latency %u",
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+ qdf_cpumask_pr_args(&hdd_ctx->qos_cpu_mask),
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+ latency);
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+ } else {
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latency = HDD_PM_QOS_HIGH_TPUT_LATENCY_US;
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-
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- for_each_cpu(cpu, &hdd_ctx->qos_cpu_mask) {
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- dev_pm_qos_update_request(&hdd_ctx->pm_qos_req[cpu],
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- latency);
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+ /* Set latency to default for CPUs not included in mask */
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+ qdf_for_each_cpu_not(cpu, &hdd_ctx->qos_cpu_mask) {
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+ dev_pm_qos_update_request(
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+ &hdd_ctx->pm_qos_req[cpu],
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+ PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE);
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+ }
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+ /* Set latency to 1 for CPUs included in mask */
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+ qdf_for_each_cpu(cpu, &hdd_ctx->qos_cpu_mask) {
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+ dev_pm_qos_update_request(
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+ &hdd_ctx->pm_qos_req[cpu],
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+ latency);
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+ }
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+ hdd_debug("For qos_cpu_mask %*pb set latency %u",
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+ qdf_cpumask_pr_args(&hdd_ctx->qos_cpu_mask),
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+ latency);
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}
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}
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