msm: camera: icp: Fix HFI init sequence
As part of HFI INIT ensure all CSR registers are configured prior to setting INIT_REQUEST. Also monitor the INIT RESPONSE status for 32 bits as opposed to 1 bit which will result in reading a false value for FW error codes > 1. CRs-Fixed: 3070374 Change-Id: Ib32f1cdf05c524072e5d6e55773351e95c9082a8 Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
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@@ -682,7 +682,7 @@ int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
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if (cam_common_read_poll_timeout(icp_base +
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HFI_REG_ICP_HOST_INIT_RESPONSE,
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HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
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0x1, ICP_INIT_RESP_SUCCESS, &status)) {
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(uint32_t)UINT_MAX, ICP_INIT_RESP_SUCCESS, &status)) {
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CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
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status);
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return -ETIMEDOUT;
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@@ -916,8 +916,6 @@ int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
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icp_base + HFI_REG_SECONDARY_HEAP_PTR);
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cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
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icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
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cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
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icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
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cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
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icp_base + HFI_REG_QDSS_IOVA);
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cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
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@@ -934,6 +932,8 @@ int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
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icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
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cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
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icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
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cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
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icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
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CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
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hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
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@@ -954,7 +954,7 @@ int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
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if (cam_common_read_poll_timeout(icp_base +
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HFI_REG_ICP_HOST_INIT_RESPONSE,
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HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
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0x1, ICP_INIT_RESP_SUCCESS, &status)) {
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(uint32_t)UINT_MAX, ICP_INIT_RESP_SUCCESS, &status)) {
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CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
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status);
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rc = -ETIMEDOUT;
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