qcacmn: Fix kernel module check patch warnings in HIF files
Fix kernel module check patch warnings in HIF files Change-Id: I3ddc76399004f15f325b56709e4f2e96bf4cda96 CRs-fixed: 2033001
此提交包含在：
Manikandan Mohan
178
hif/inc/hif.h
178
hif/inc/hif.h
@@ -48,7 +48,6 @@ extern "C" {
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#endif
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#define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
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typedef struct htc_callbacks HTC_CALLBACKS;
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typedef void __iomem *A_target_id_t;
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typedef void *hif_handle_t;
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@@ -181,7 +180,8 @@ struct CE_state;
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#define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
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/* NOTE: "napi->scale" can be changed,
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but this does not change the number of buckets */
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* but this does not change the number of buckets
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*/
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#define QCA_NAPI_NUM_BUCKETS 4
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struct qca_napi_stat {
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uint32_t napi_schedules;
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@@ -203,7 +203,7 @@ struct qca_napi_stat {
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*/
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struct qca_napi_info {
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struct net_device netdev; /* dummy net_dev */
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void *hif_ctx;
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void *hif_ctx;
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struct napi_struct napi;
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uint8_t scale; /* currently same on all instances */
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uint8_t id;
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@@ -211,7 +211,7 @@ struct qca_napi_info {
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int irq;
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struct qca_napi_stat stats[NR_CPUS];
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/* will only be present for data rx CE's */
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void (*lro_flush_cb)(void *);
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void (*lro_flush_cb)(void *arg);
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void *lro_ctx;
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qdf_spinlock_t lro_unloading_lock;
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};
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@@ -262,10 +262,10 @@ struct qca_napi_cpu {
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struct qca_napi_data {
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qdf_spinlock_t lock;
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uint32_t state;
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uint32_t ce_map; /* bitmap of created/registered NAPI
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instances, indexed by pipe_id,
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not used by clients (clients use an
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id returned by create) */
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/* bitmap of created/registered NAPI instances, indexed by pipe_id,
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* not used by clients (clients use an id returned by create)
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*/
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uint32_t ce_map;
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struct qca_napi_info napis[CE_COUNT_MAX];
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struct qca_napi_cpu napi_cpu[NR_CPUS];
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int lilcl_head, bigcl_head;
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@@ -308,17 +308,22 @@ struct hif_target_info {
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struct hif_opaque_softc {
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};
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typedef enum {
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HIF_DEVICE_POWER_UP, /* HIF layer should power up interface
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* and/or module */
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HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific
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* measures to minimize power */
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HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific
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* AND/OR platform-specific measures
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* to completely power-off the module and
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* associated hardware (i.e. cut power
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* supplies) */
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} HIF_DEVICE_POWER_CHANGE_TYPE;
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/**
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* enum HIF_DEVICE_POWER_CHANGE_TYPE: Device Power change type
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*
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* @HIF_DEVICE_POWER_UP: HIF layer should power up interface and/or module
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* @HIF_DEVICE_POWER_DOWN: HIF layer should initiate bus-specific measures to
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* minimize power
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* @HIF_DEVICE_POWER_CUT: HIF layer should initiate bus-specific AND/OR
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* platform-specific measures to completely power-off
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* the module and associated hardware (i.e. cut power
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* supplies)
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*/
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enum HIF_DEVICE_POWER_CHANGE_TYPE {
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HIF_DEVICE_POWER_UP,
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HIF_DEVICE_POWER_DOWN,
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HIF_DEVICE_POWER_CUT
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};
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/**
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* enum hif_enable_type: what triggered the enabling of hif
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@@ -336,8 +341,7 @@ enum hif_enable_type {
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* enum hif_disable_type: what triggered the disabling of hif
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*
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* @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
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* @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered
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* disable
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* @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered disable
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* @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
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* @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
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*/
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@@ -386,12 +390,12 @@ enum hif_device_config_opcode {
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};
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#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
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typedef struct _HID_ACCESS_LOG {
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struct HID_ACCESS_LOG {
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uint32_t seqnum;
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bool is_write;
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void *addr;
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uint32_t value;
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} HIF_ACCESS_LOG;
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};
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#endif
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void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset,
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@@ -399,11 +403,16 @@ void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset,
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uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset);
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#define HIF_MAX_DEVICES 1
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/**
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* struct htc_callbacks - Structure for HTC Callbacks methods
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* @context: context to pass to the dsrhandler
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* note : rwCompletionHandler is provided the context
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* passed to hif_read_write
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* @rwCompletionHandler: Read / write completion handler
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* @dsrHandler: DSR Handler
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*/
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struct htc_callbacks {
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void *context; /* context to pass to the dsrhandler
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* note : rwCompletionHandler is provided
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* the context passed to hif_read_write */
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void *context;
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QDF_STATUS(*rwCompletionHandler)(void *rwContext, QDF_STATUS status);
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QDF_STATUS(*dsrHandler)(void *context);
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};
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@@ -428,7 +437,7 @@ struct hif_driver_state_callbacks {
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};
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/* This API detaches the HTC layer from the HIF device */
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void hif_detach_htc(struct hif_opaque_softc *scn);
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void hif_detach_htc(struct hif_opaque_softc *hif_ctx);
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/****************************************************************/
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/* BMI and Diag window abstraction */
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@@ -438,12 +447,14 @@ void hif_detach_htc(struct hif_opaque_softc *scn);
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#define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be
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* handled atomically by
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* DiagRead/DiagWrite */
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* DiagRead/DiagWrite
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*/
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/*
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* API to handle HIF-specific BMI message exchanges, this API is synchronous
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* and only allowed to be called from a context that can block (sleep) */
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QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *scn,
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* and only allowed to be called from a context that can block (sleep)
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*/
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QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
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qdf_dma_addr_t cmd, qdf_dma_addr_t rsp,
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uint8_t *pSendMessage, uint32_t Length,
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uint8_t *pResponseMessage,
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@@ -459,12 +470,12 @@ QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *scn,
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*
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* hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
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*/
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QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *scn, uint32_t address,
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uint32_t *data);
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QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *scn, uint32_t address,
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QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
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uint32_t address, uint32_t *data);
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QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address,
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uint8_t *data, int nbytes);
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void hif_dump_target_memory(struct hif_opaque_softc *scn, void *ramdump_base,
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uint32_t address, uint32_t size);
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void hif_dump_target_memory(struct hif_opaque_softc *hif_ctx,
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void *ramdump_base, uint32_t address, uint32_t size);
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/*
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* APIs to handle HIF specific diagnostic write accesses. These APIs are
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* synchronous and only allowed to be called from a context that
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@@ -476,10 +487,10 @@ void hif_dump_target_memory(struct hif_opaque_softc *scn, void *ramdump_base,
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*
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* hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
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*/
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QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *scn, uint32_t address,
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uint32_t data);
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QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *scn, uint32_t address,
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uint8_t *data, int nbytes);
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QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx,
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uint32_t address, uint32_t data);
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QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx,
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uint32_t address, uint8_t *data, int nbytes);
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typedef void (*fastpath_msg_handler)(void *, qdf_nbuf_t *, uint32_t);
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typedef uint32_t (*ext_intr_handler)(void *, uint32_t);
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@@ -514,7 +525,7 @@ static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret)
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*/
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#define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
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void hif_ipa_get_ce_resource(struct hif_opaque_softc *scn,
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void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx,
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qdf_dma_addr_t *ce_sr_base_paddr,
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uint32_t *ce_sr_ring_size,
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qdf_dma_addr_t *ce_reg_paddr);
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@@ -596,52 +607,51 @@ struct hif_pipe_addl_info {
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};
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struct hif_bus_id;
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typedef struct hif_bus_id hif_bus_id;
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void hif_claim_device(struct hif_opaque_softc *hif_ctx);
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QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx,
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int opcode, void *config, uint32_t config_len);
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void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx);
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void hif_mask_interrupt_call(struct hif_opaque_softc *scn);
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void hif_post_init(struct hif_opaque_softc *scn, void *hHTC,
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void hif_mask_interrupt_call(struct hif_opaque_softc *hif_ctx);
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void hif_post_init(struct hif_opaque_softc *hif_ctx, void *hHTC,
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struct hif_msg_callbacks *callbacks);
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QDF_STATUS hif_start(struct hif_opaque_softc *scn);
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void hif_stop(struct hif_opaque_softc *scn);
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void hif_flush_surprise_remove(struct hif_opaque_softc *scn);
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void hif_dump(struct hif_opaque_softc *scn, uint8_t CmdId, bool start);
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QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx);
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void hif_stop(struct hif_opaque_softc *hif_ctx);
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void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx);
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void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t CmdId, bool start);
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void hif_trigger_dump(struct hif_opaque_softc *hif_ctx,
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uint8_t cmd_id, bool start);
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QDF_STATUS hif_send_head(struct hif_opaque_softc *scn, uint8_t PipeID,
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QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
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uint32_t transferID, uint32_t nbytes,
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qdf_nbuf_t wbuf, uint32_t data_attr);
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void hif_send_complete_check(struct hif_opaque_softc *scn, uint8_t PipeID,
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void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t PipeID,
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int force);
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void hif_shut_down_device(struct hif_opaque_softc *scn);
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void hif_get_default_pipe(struct hif_opaque_softc *scn, uint8_t *ULPipe,
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void hif_shut_down_device(struct hif_opaque_softc *hif_ctx);
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void hif_get_default_pipe(struct hif_opaque_softc *hif_ctx, uint8_t *ULPipe,
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uint8_t *DLPipe);
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int hif_map_service_to_pipe(struct hif_opaque_softc *scn, uint16_t svc_id,
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int hif_map_service_to_pipe(struct hif_opaque_softc *hif_ctx, uint16_t svc_id,
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uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
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int *dl_is_polled);
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uint16_t
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hif_get_free_queue_number(struct hif_opaque_softc *scn, uint8_t PipeID);
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void *hif_get_targetdef(struct hif_opaque_softc *scn);
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hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t PipeID);
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void *hif_get_targetdef(struct hif_opaque_softc *hif_ctx);
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uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
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void hif_set_target_sleep(struct hif_opaque_softc *scn, bool sleep_ok,
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void hif_set_target_sleep(struct hif_opaque_softc *hif_ctx, bool sleep_ok,
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bool wait_for_it);
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int hif_check_fw_reg(struct hif_opaque_softc *scn);
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int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx);
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#ifndef HIF_PCI
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static inline int hif_check_soc_status(struct hif_opaque_softc *scn)
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static inline int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
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{
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return 0;
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}
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#else
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int hif_check_soc_status(struct hif_opaque_softc *scn);
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int hif_check_soc_status(struct hif_opaque_softc *hif_ctx);
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#endif
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void hif_get_hw_info(struct hif_opaque_softc *scn, u32 *version, u32 *revision,
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const char **target_name);
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void hif_disable_isr(struct hif_opaque_softc *scn);
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void hif_reset_soc(struct hif_opaque_softc *scn);
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void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
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u32 *revision, const char **target_name);
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void hif_disable_isr(struct hif_opaque_softc *hif_ctx);
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void hif_reset_soc(struct hif_opaque_softc *hif_ctx);
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void hif_save_htc_htt_config_endpoint(struct hif_opaque_softc *hif_ctx,
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int htc_htt_tx_endpoint);
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struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx, uint32_t mode,
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@@ -649,7 +659,7 @@ struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx, uint32_t mode,
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struct hif_driver_state_callbacks *cbk);
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void hif_close(struct hif_opaque_softc *hif_ctx);
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QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev,
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void *bdev, const hif_bus_id *bid,
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void *bdev, const struct hif_bus_id *bid,
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enum qdf_bus_type bus_type,
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enum hif_enable_type type);
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void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type);
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@@ -705,9 +715,9 @@ void hif_enable_power_management(struct hif_opaque_softc *hif_ctx,
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bool is_packet_log_enabled);
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void hif_disable_power_management(struct hif_opaque_softc *hif_ctx);
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void hif_vote_link_down(struct hif_opaque_softc *);
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void hif_vote_link_up(struct hif_opaque_softc *);
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bool hif_can_suspend_link(struct hif_opaque_softc *);
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void hif_vote_link_down(struct hif_opaque_softc *hif_ctx);
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void hif_vote_link_up(struct hif_opaque_softc *hif_ctx);
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bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx);
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#ifdef IPA_OFFLOAD
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/**
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@@ -723,7 +733,7 @@ enum ipa_hw_type hif_get_ipa_hw_type(void)
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return ipa_get_hw_type();
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}
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#endif
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int hif_bus_resume(struct hif_opaque_softc *);
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int hif_bus_resume(struct hif_opaque_softc *hif_ctx);
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/**
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* hif_bus_ealry_suspend() - stop non wmi tx traffic
|
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* @context: hif context
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@@ -735,9 +745,9 @@ int hif_bus_early_suspend(struct hif_opaque_softc *hif_ctx);
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* @context: hif context
|
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*/
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int hif_bus_late_resume(struct hif_opaque_softc *hif_ctx);
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int hif_bus_suspend(struct hif_opaque_softc *);
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int hif_bus_resume_noirq(struct hif_opaque_softc *);
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int hif_bus_suspend_noirq(struct hif_opaque_softc *);
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int hif_bus_suspend(struct hif_opaque_softc *hif_ctx);
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int hif_bus_resume_noirq(struct hif_opaque_softc *hif_ctx);
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int hif_bus_suspend_noirq(struct hif_opaque_softc *hif_ctx);
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/**
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* hif_apps_irqs_enable() - Enables all irqs from the APPS side
|
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@@ -788,27 +798,27 @@ int hif_pre_runtime_suspend(struct hif_opaque_softc *hif_ctx);
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void hif_pre_runtime_resume(struct hif_opaque_softc *hif_ctx);
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int hif_runtime_suspend(struct hif_opaque_softc *hif_ctx);
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int hif_runtime_resume(struct hif_opaque_softc *hif_ctx);
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void hif_process_runtime_suspend_success(struct hif_opaque_softc *);
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void hif_process_runtime_suspend_failure(struct hif_opaque_softc *);
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void hif_process_runtime_resume_success(struct hif_opaque_softc *);
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void hif_process_runtime_suspend_success(struct hif_opaque_softc *hif_ctx);
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void hif_process_runtime_suspend_failure(struct hif_opaque_softc *hif_ctx);
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void hif_process_runtime_resume_success(struct hif_opaque_softc *hif_ctx);
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#endif
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|
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int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size);
|
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int hif_dump_registers(struct hif_opaque_softc *scn);
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int ol_copy_ramdump(struct hif_opaque_softc *scn);
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||||
void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx);
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void hif_get_hw_info(struct hif_opaque_softc *scn, u32 *version, u32 *revision,
|
||||
const char **target_name);
|
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void hif_lro_flush_cb_register(struct hif_opaque_softc *scn,
|
||||
void (lro_flush_handler)(void *),
|
||||
void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version,
|
||||
u32 *revision, const char **target_name);
|
||||
void hif_lro_flush_cb_register(struct hif_opaque_softc *hif_ctx,
|
||||
void (lro_flush_handler)(void *arg),
|
||||
void *(lro_init_handler)(void));
|
||||
void hif_lro_flush_cb_deregister(struct hif_opaque_softc *scn,
|
||||
void (lro_deinit_cb)(void *));
|
||||
bool hif_needs_bmi(struct hif_opaque_softc *scn);
|
||||
void hif_lro_flush_cb_deregister(struct hif_opaque_softc *hif_ctx,
|
||||
void (lro_deinit_cb)(void *arg));
|
||||
bool hif_needs_bmi(struct hif_opaque_softc *hif_ctx);
|
||||
enum qdf_bus_type hif_get_bus_type(struct hif_opaque_softc *hif_hdl);
|
||||
struct hif_target_info *hif_get_target_info_handle(struct hif_opaque_softc *
|
||||
scn);
|
||||
struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *scn);
|
||||
struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *hif_ctx);
|
||||
struct ramdump_info *hif_get_ramdump_ctx(struct hif_opaque_softc *hif_ctx);
|
||||
enum hif_target_status hif_get_target_status(struct hif_opaque_softc *hif_ctx);
|
||||
void hif_set_target_status(struct hif_opaque_softc *hif_ctx, enum
|
||||
@@ -834,9 +844,9 @@ uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc,
|
||||
int32_t hif_get_nss_wifiol_bypass_nw_process(struct hif_opaque_softc *osc);
|
||||
#endif /* QCA_NSS_WIFI_OFFLOAD_SUPPORT */
|
||||
|
||||
void hif_set_bundle_mode(struct hif_opaque_softc *scn, bool enabled,
|
||||
void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled,
|
||||
int rx_bundle_cnt);
|
||||
int hif_bus_reset_resume(struct hif_opaque_softc *scn);
|
||||
int hif_bus_reset_resume(struct hif_opaque_softc *hif_ctx);
|
||||
|
||||
void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib);
|
||||
|
||||
|
||||
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