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disp: msm: sde: fix cwb, dp and wb tear down sequence

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CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.

Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This commit is contained in:
Dhaval Patel
2019-07-09 16:29:11 -07:00
parent 84fc2163e1
commit bcd97aa368
7 changed files with 73 additions and 55 deletions
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46
msm/sde/sde_hw_ctl.c
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@@ -1012,12 +1012,8 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx)
{
struct sde_hw_blk_reg_map *c;
u32 intf_active = 0;
u32 intf_flush = 0;
u32 merge_3d_active = 0;
u32 merge_3d_flush = 0;
u32 wb_active = 0;
u32 wb_flush = 0;
u32 intf_active = 0, wb_active = 0, merge_3d_active = 0;
u32 intf_flush = 0, wb_flush = 0;
u32 i;
if (!ctx || !cfg) {
@@ -1042,25 +1038,30 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
if (merge_3d_idx) {
/* disable and flush merge3d_blk */
merge_3d_flush = BIT(merge_3d_idx - MERGE_3D_0);
ctx->flush.pending_merge_3d_flush_mask =
BIT(merge_3d_idx - MERGE_3D_0);
merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
ctx->flush.pending_merge_3d_flush_mask = merge_3d_flush;
SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
}
sde_hw_ctl_clear_all_blendstages(ctx);
ctx->flush.pending_intf_flush_mask = intf_flush;
ctx->flush.pending_wb_flush_mask = wb_flush;
SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
if (cfg->intf_count) {
ctx->flush.pending_intf_flush_mask = intf_flush;
UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
}
if (cfg->wb_count) {
ctx->flush.pending_wb_flush_mask = wb_flush;
UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
}
return 0;
}
static int sde_hw_ctl_update_cwb_cfg(struct sde_hw_ctl *ctx,
struct sde_hw_intf_cfg_v1 *cfg)
struct sde_hw_intf_cfg_v1 *cfg, bool enable)
{
int i;
u32 cwb_active = 0;
@@ -1084,11 +1085,16 @@ static int sde_hw_ctl_update_cwb_cfg(struct sde_hw_ctl *ctx,
merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
}
wb_active = BIT(2);
SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
if (enable) {
wb_active = BIT(2);
SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
} else {
SDE_REG_WRITE(c, CTL_WB_ACTIVE, 0x0);
SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, 0x0);
SDE_REG_WRITE(c, CTL_CWB_ACTIVE, 0x0);
}
return 0;
}