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disp: msm: sde: fix cwb, dp and wb tear down sequence

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CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.

Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This commit is contained in:
Dhaval Patel
2019-07-09 16:29:11 -07:00
parent 84fc2163e1
commit bcd97aa368
7 changed files with 73 additions and 55 deletions
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39
msm/sde/sde_encoder.c
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@@ -3383,10 +3383,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
{
struct sde_encoder_virt *sde_enc;
if (wb_enc) {
if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
return;
phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
sde_encoder_helper_reset_mixers(phys_enc, NULL);
if (wb_enc) {
if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
false, phys_enc->hw_pp->idx);
@@ -4182,34 +4182,22 @@ void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
struct sde_encoder_phys *phys;
unsigned int i;
struct sde_hw_ctl *ctl;
struct msm_display_info *disp_info;
if (!drm_enc) {
SDE_ERROR("invalid encoder\n");
return;
}
sde_enc = to_sde_encoder_virt(drm_enc);
disp_info = &sde_enc->disp_info;
for (i = 0; i < sde_enc->num_phys_encs; i++) {
phys = sde_enc->phys_encs[i];
if (phys && phys->hw_ctl) {
if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
sde_encoder_check_curr_mode(drm_enc,
MSM_DISPLAY_CMD_MODE)) {
ctl = phys->hw_ctl;
/*
* avoid clearing the pending flush during the first
* frame update after idle power collpase as the
* restore path would have updated the pending flush
*/
if (!sde_enc->idle_pc_restore &&
ctl->ops.clear_pending_flush)
ctl->ops.clear_pending_flush(ctl);
if (ctl->ops.trigger_pending)
/* update only for command mode primary ctl */
if ((phys == sde_enc->cur_master) &&
(sde_encoder_check_curr_mode(drm_enc,
MSM_DISPLAY_CMD_MODE))
&& ctl->ops.trigger_pending)
ctl->ops.trigger_pending(ctl);
}
}
@@ -4934,6 +4922,7 @@ void sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
struct sde_encoder_virt *sde_enc;
struct sde_encoder_phys *phys;
int i;
struct sde_hw_ctl *ctl;
if (!drm_enc) {
SDE_ERROR("invalid encoder\n");
@@ -4945,6 +4934,18 @@ void sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
phys = sde_enc->phys_encs[i];
if (phys && phys->ops.prepare_commit)
phys->ops.prepare_commit(phys);
if (phys && phys->hw_ctl) {
ctl = phys->hw_ctl;
/*
* avoid clearing the pending flush during the first
* frame update after idle power collpase as the
* restore path would have updated the pending flush
*/
if (!sde_enc->idle_pc_restore &&
ctl->ops.clear_pending_flush)
ctl->ops.clear_pending_flush(ctl);
}
}
}