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qcacmn: Do not allow CE register access when recovery is in progress

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Currently, Shadow registers is not implemented for all registers.
This can lead to unclocked access and followed by NOC errors.
In Rx path Interrupt Status and src/dst read index are directly
accessed without shadow block. Target may execute
reset sequence due to PDR/SSR while rx path is active.

Avoid direct access to below registers if target is crashed due
to PDR/SSR.

HOST_IE_ADDRESS
HOST_IS_ADDRESS
CURRENT_DRRI_ADDRESS
CURRENT_SRRI_ADDRESS

Return from ISR without scheduling the bottom half if target is
crashed due to PDR/SSR.

Change-Id: Ifa993e978579b4d061d21281338494292e19700a
CRs-Fixed: 2123967
This commit is contained in:
Govind Singh
2017-06-08 12:33:59 +05:30
committed by Nandini Suresh
parent 4a2f03c01c
commit bc679dc919
9 changed files with 103 additions and 14 deletions
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2
hif/src/hif_io32.h
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@@ -40,6 +40,8 @@
hif_target_sleep_state_adjust(scn, false, true)
#define Q_TARGET_ACCESS_END(scn) \
hif_target_sleep_state_adjust(scn, true, false)
#define TARGET_REGISTER_ACCESS_ALLOWED(scn)\
hif_is_target_register_access_allowed(scn)
/*
* A_TARGET_ACCESS_LIKELY will not wait for the target to wake up before