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qcacmn: Add support for DS UL processing

Add support for PPE-DS REO2PPE ring processing

Change-Id: I74f4195ce4a58d1afaef132257b969ce38a65e1c
CRs-Fixed: 3278270
Este cometimento está contido em:
Manish Verma
2022-07-20 17:03:23 +05:30
cometido por Madan Koyyalamudi
ascendente 8aa059674f
cometimento bc05063ebb
4 ficheiros modificados com 65 adições e 4 eliminações

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@@ -3304,4 +3304,64 @@ void *hal_srng_dst_get_next_32_byte_desc(hal_soc_handle_t hal_soc_hdl,
return (void *)last_prefetched_hw_desc; return (void *)last_prefetched_hw_desc;
} }
/**
* hal_srng_src_set_hp() - set head idx.
* @hal_soc_hdl: HAL SOC handle
* @idx: head idx
*
* return: none
*/
static inline
void hal_srng_src_set_hp(hal_ring_handle_t hal_ring_hdl, uint16_t idx)
{
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
srng->u.src_ring.hp = idx * srng->entry_size;
}
/**
* hal_srng_dst_set_tp() - set tail idx.
* @hal_soc_hdl: HAL SOC handle
* @idx: tail idx
*
* return: none
*/
static inline
void hal_srng_dst_set_tp(hal_ring_handle_t hal_ring_hdl, uint16_t idx)
{
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
srng->u.dst_ring.tp = idx * srng->entry_size;
}
/**
* hal_srng_src_get_tpidx() - get tail idx
* @hal_soc_hdl: HAL SOC handle
*
* return: tail idx
*/
static inline
uint16_t hal_srng_src_get_tpidx(hal_ring_handle_t hal_ring_hdl)
{
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
uint32_t tp = *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
return tp / srng->entry_size;
}
/**
* hal_srng_dst_get_hpidx() - get head idx
* @hal_soc_hdl: HAL SOC handle
*
* return: head idx
*/
static inline
uint16_t hal_srng_dst_get_hpidx(hal_ring_handle_t hal_ring_hdl)
{
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
uint32_t hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
return hp / srng->entry_size;
}
#endif /* _HAL_APIH_ */ #endif /* _HAL_APIH_ */

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@@ -1470,7 +1470,8 @@ struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
/* /*
* REO2PPE destination indication * REO2PPE destination indication
*/ */
#define REO2PPE_DST_IND 11 #define REO2PPE_DST_IND 6
#define REO2PPE_DST_RING 11
#define REO2PPE_RULE_FAIL_FB 0x2000 #define REO2PPE_RULE_FAIL_FB 0x2000
/** /**

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@@ -1422,7 +1422,7 @@ void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc)
(REO_REG_REG_BASE)); (REO_REG_REG_BASE));
remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6));
remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_IND, 6); remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6);
HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
(REO_REG_REG_BASE), remap0); (REO_REG_REG_BASE), remap0);

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@@ -442,9 +442,9 @@
#define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1
#define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4
#define WLAN_CFG_REO2PPE_RING_SIZE 1024 #define WLAN_CFG_REO2PPE_RING_SIZE 2048
#define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64
#define WLAN_CFG_REO2PPE_RING_SIZE_MAX 1024 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 16384
#define WLAN_CFG_PPE2TCL_RING_SIZE 1024 #define WLAN_CFG_PPE2TCL_RING_SIZE 1024
#define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64