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disp: msm: sde: allow frame_done count to reach till 2

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A frame trigger with posted start may have two frames
in wait state due to irq disable on that CPU. In such
case, frame_done count can reach till 2. Allowing count
only till 1, can cause the release_fence trigger miss
and a buffer is held by DPU driver.

Change-Id: I42c10b064ebcaff136591975f3010c11f99a0731
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This commit is contained in:
Dhaval Patel
2020-06-11 16:38:08 -07:00
parent fae3dc03b4
commit bbcb96a8e5
1 changed files with 4 additions and 3 deletions
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7
msm/sde/sde_encoder.c
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@@ -3101,7 +3101,7 @@ static void sde_encoder_frame_done_callback(
SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
atomic_read(&sde_enc->frame_done_cnt[i]));
if (!atomic_add_unless(
&sde_enc->frame_done_cnt[i], 1, 1)) {
&sde_enc->frame_done_cnt[i], 1, 2)) {
SDE_EVT32(DRMID(drm_enc), event,
ready_phys->intf_idx,
SDE_EVTLOG_ERROR);
@@ -3113,7 +3113,7 @@ static void sde_encoder_frame_done_callback(
}
if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
atomic_read(&sde_enc->frame_done_cnt[i]) != 1)
atomic_read(&sde_enc->frame_done_cnt[i]) == 0)
trigger = false;
}
@@ -3123,7 +3123,8 @@ static void sde_encoder_frame_done_callback(
&sde_enc->crtc_frame_event_cb_data,
event);
for (i = 0; i < sde_enc->num_phys_encs; i++)
atomic_set(&sde_enc->frame_done_cnt[i], 0);
atomic_add_unless(&sde_enc->frame_done_cnt[i],
-1, 0);
}
} else if (sde_enc->crtc_frame_event_cb) {
sde_enc->crtc_frame_event_cb(