disp: pll: Fix cfg1 value when pclk_src_mux parent is updated

Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated.

Change-Id: I1e45ff0685797bf4dd2e3a52af4753425f31edfc
Signed-off-by: Ritesh Kumar <[email protected]>

msm/dsi/dsi_pll_5nm.c

@@ -374,6 +374,12 @@ static inline int pclk_mux_read_sel(void *context, unsigned int reg,
 	int rc = 0;
 	struct dsi_pll_resource *rsc = context;
 
+	/* Return cached cfg1 as its updated with cached cfg1 in pll_enable */
+	if (!rsc->handoff_resources) {
+		*val = (rsc->cached_cfg1) & 0x3;
+		return rc;
+	}
+
 	*val = (DSI_PLL_REG_R(rsc->phy_base, reg) & 0x3);
 
 	return rc;