From ba3d7304f5d3d88a4f31d74f314bca630621ea07 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 20 Oct 2020 16:06:12 +0530 Subject: [PATCH] disp: pll: Fix cfg1 value when pclk_src_mux parent is updated Currently, PLL_CFG1(1:0) register is updated with cached values in dsi_pll_enable. This can create issue when UEFI and kernel cfg1 programming is not same. To fix it, return cached value of cfg1 when its read in pclk_mux_read, so that pclk_mux_write is called and cached value is updated. Change-Id: I1e45ff0685797bf4dd2e3a52af4753425f31edfc Signed-off-by: Ritesh Kumar --- msm/dsi/dsi_pll_5nm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/msm/dsi/dsi_pll_5nm.c b/msm/dsi/dsi_pll_5nm.c index dcfbda5a9e..6990a934aa 100644 --- a/msm/dsi/dsi_pll_5nm.c +++ b/msm/dsi/dsi_pll_5nm.c @@ -374,6 +374,12 @@ static inline int pclk_mux_read_sel(void *context, unsigned int reg, int rc = 0; struct dsi_pll_resource *rsc = context; + /* Return cached cfg1 as its updated with cached cfg1 in pll_enable */ + if (!rsc->handoff_resources) { + *val = (rsc->cached_cfg1) & 0x3; + return rc; + } + *val = (DSI_PLL_REG_R(rsc->phy_base, reg) & 0x3); return rc;