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@@ -25,12 +25,12 @@
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#include "qdf_nbuf.h"
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#include "../../wlan_cfg/wlan_cfg.h"
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-#ifdef TX_CORE_ALIGNED_SEND
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-#define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
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-#define DP_TX_GET_RING_ID(vdev) qdf_get_cpu()
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-#else
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+#ifdef TX_PER_VDEV_DESC_POOL
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#define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
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#define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
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+#else
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+#define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
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+#define DP_TX_GET_RING_ID(vdev) qdf_get_cpu()
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#endif /* TX_CORE_ALIGNED_SEND */
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/* TODO Add support in TSO */
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@@ -229,6 +229,7 @@ struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
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/* Allocate an extension descriptor */
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msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
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+ qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXTENSION_DESC_LEN_BYTES);
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if (!msdu_ext_desc)
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return NULL;
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@@ -310,13 +311,16 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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tx_desc->vdev = vdev;
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tx_desc->msdu_ext_desc = NULL;
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- /*
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- * For non-scatter regular frames, buffer pointer is directly
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- * programmed in TCL input descriptor instead of using an MSDU extension
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- * descriptor.For the direct buffer pointer case, HW requirement is that
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- * descriptor should always point to a 8-byte aligned address.
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- */
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- align_pad = (uint8_t)((uintptr_t) (qdf_nbuf_data(nbuf)) & 0x7);
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+ if (qdf_nbuf_map_nbytes_single(soc->osdev, nbuf,
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+ QDF_DMA_TO_DEVICE, qdf_nbuf_len(nbuf)
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+ != QDF_STATUS_SUCCESS)) {
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+ /* Handle failure */
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+ QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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+ "qdf_nbuf_map_nbytes_single failed\n");
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+ goto failure;
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+ }
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+
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+ align_pad = ((unsigned long) qdf_nbuf_mapped_paddr_get(nbuf)) & 0x7;
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tx_desc->pkt_offset = align_pad;
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/*
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@@ -326,7 +330,8 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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* These are filled in HTT MSDU descriptor and sent in frame pre-header.
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* These frames are sent as exception packets to firmware.
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*/
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- if (qdf_unlikely(vdev->mesh_vdev || (vdev->opmode == wlan_op_mode_ocb))) {
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+ if (qdf_unlikely(vdev->mesh_vdev ||
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+ (vdev->opmode == wlan_op_mode_ocb))) {
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htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
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align_pad);
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tx_desc->pkt_offset += htt_hdr_size;
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@@ -353,15 +358,6 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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pdev->num_tx_exception++;
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}
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- if (qdf_nbuf_map_nbytes_single(soc->osdev, nbuf,
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- QDF_DMA_TO_DEVICE, qdf_nbuf_len(nbuf)
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- != QDF_STATUS_SUCCESS)) {
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- /* Handle failure */
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- QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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- "qdf_nbuf_map_nbytes_single failed\n");
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- goto failure;
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- }
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-
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return tx_desc;
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failure:
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@@ -497,14 +493,20 @@ QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
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} else {
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length = qdf_nbuf_len(tx_desc->nbuf);
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type = HAL_TX_BUF_TYPE_BUFFER;
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- dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
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+
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+ /**
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+ * For non-scatter regular frames, buffer pointer is directly
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+ * programmed in TCL input descriptor instead of using an MSDU
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+ * extension descriptor.For the direct buffer pointer case, HW
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+ * requirement is that descriptor should always point to a
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+ * 8-byte aligned address.
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+ * Alignment padding is already accounted in pkt_offset
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+ *
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+ */
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+ dma_addr = (qdf_nbuf_mapped_paddr_get(tx_desc->nbuf) -
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+ tx_desc->pkt_offset);
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}
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- /*
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- * Address given to TCL should always be 8-byte aligned.
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- * Alignment bytes are already accounted in length as pkt_offset
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- */
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- dma_addr -= ((uint32_t) dma_addr & 0x7);
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hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
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hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
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@@ -515,7 +517,8 @@ QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
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"%s length:%d , type = %d, dma_addr %llx, offset %d\n",
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- __func__, length, type, (uint64_t)dma_addr, tx_desc->pkt_offset);
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+ __func__, length, type, (uint64_t)dma_addr,
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+ tx_desc->pkt_offset);
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if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
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hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
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@@ -841,6 +844,12 @@ qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
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*/
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dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
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+ /*
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+ * Set Default Host TID value to invalid TID
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+ * (TID override disabled)
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+ */
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+ msdu_info.tid = HTT_TX_EXT_TID_INVALID;
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+
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/*
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* TCL H/W supports 2 DSCP-TID mapping tables.
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* Table 1 - Default DSCP-TID mapping table
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@@ -1226,17 +1235,18 @@ uint32_t dp_tx_comp_handler(struct dp_soc *soc, uint32_t ring_id,
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/* First ring descriptor on the cycle */
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if (!head_desc) {
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head_desc = tx_desc;
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- tail_desc = tx_desc;
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+ } else {
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+ tail_desc->next = tx_desc;
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}
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- tail_desc->next = tx_desc;
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+ tail_desc = tx_desc;
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/* Collect hw completion contents */
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hal_tx_comp_desc_sync(tx_comp_hal_desc,
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&tx_desc->comp, soc->process_tx_status);
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+
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}
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- tail_desc = tx_desc;
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num_processed++;
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/*
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