Merge e409b8c5d28a1d755d06779aa2a338e04ac72984 on remote branch

Change-Id: I77ad242b32a123e3c131899c20818dbfc851ad43

Kbuild

@@ -79,7 +79,7 @@ KBUILD_CPPFLAGS += -DCONFIG_CNSS2_ENUM_WITH_LOW_SPEED
 endif
 
 ifeq ($(CONFIG_SLATE_MODULE_ENABLED), y)
-KBUILD_CPPFLAGS += -DSLATE_MODULE_ENABLED
+KBUILD_CPPFLAGS += -DCONFIG_SLATE_MODULE_ENABLED
 endif
 
 obj-$(CONFIG_CNSS2) += cnss2/

cnss2/main.c

@@ -443,6 +443,51 @@ static int cnss_get_audio_iommu_domain(struct cnss_plat_data *plat_priv)
 	return 0;
 }
 
+bool cnss_get_audio_shared_iommu_group_cap(struct device *dev)
+{
+	struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
+	struct device_node *audio_ion_node;
+	struct device_node *cnss_iommu_group_node;
+	struct device_node *audio_iommu_group_node;
+
+	if (!plat_priv)
+		return false;
+
+	audio_ion_node = of_find_compatible_node(NULL, NULL,
+						 "qcom,msm-audio-ion");
+	if (!audio_ion_node) {
+		cnss_pr_err("Unable to get Audio ion node");
+		return false;
+	}
+
+	audio_iommu_group_node = of_parse_phandle(audio_ion_node,
+						  "qcom,iommu-group", 0);
+	of_node_put(audio_ion_node);
+	if (!audio_iommu_group_node) {
+		cnss_pr_err("Unable to get audio iommu group phandle");
+		return false;
+	}
+	of_node_put(audio_iommu_group_node);
+
+	cnss_iommu_group_node = of_parse_phandle(dev->of_node,
+						 "qcom,iommu-group", 0);
+	if (!cnss_iommu_group_node) {
+		cnss_pr_err("Unable to get cnss iommu group phandle");
+		return false;
+	}
+	of_node_put(cnss_iommu_group_node);
+
+	if (cnss_iommu_group_node == audio_iommu_group_node) {
+		plat_priv->is_audio_shared_iommu_group = true;
+		cnss_pr_info("CNSS and Audio share IOMMU group");
+	} else {
+		cnss_pr_info("CNSS and Audio do not share IOMMU group");
+	}
+
+	return plat_priv->is_audio_shared_iommu_group;
+}
+EXPORT_SYMBOL(cnss_get_audio_shared_iommu_group_cap);
+
 int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
 			  enum cnss_feature_v01 feature)
 {
@@ -752,6 +797,9 @@ int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
 	if (!plat_priv->audio_iommu_domain)
 		return -EINVAL;
 
+	if (plat_priv->is_audio_shared_iommu_group)
+		return 0;
+
 	page_offset = iova & (PAGE_SIZE - 1);
 	if (page_offset + size > PAGE_SIZE)
 		size += PAGE_SIZE;
@@ -770,10 +818,8 @@ void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
 	struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
 	uint32_t page_offset;
 
-	if (!plat_priv)
-		return;
-
-	if (!plat_priv->audio_iommu_domain)
+	if (!plat_priv || !plat_priv->audio_iommu_domain ||
+	    plat_priv->is_audio_shared_iommu_group)
 		return;
 
 	page_offset = iova & (PAGE_SIZE - 1);

cnss2/main.h

@@ -613,6 +613,7 @@ struct cnss_plat_data {
 	u64 fw_caps;
 	u8 pcie_gen_speed;
 	struct iommu_domain *audio_iommu_domain;
+	bool is_audio_shared_iommu_group;
 	struct cnss_dms_data dms;
 	int power_up_error;
 	u32 hw_trc_override;

cnss2/pci.c

@@ -4301,9 +4301,6 @@ static int cnss_pci_runtime_resume(struct device *dev)
 	else
 		ret = cnss_auto_resume(dev);
 
-	if (!ret)
-		pci_priv->drv_connected_last = 0;
-
 	cnss_pr_vdbg("Runtime resume status: %d\n", ret);
 
 	return ret;
@@ -4572,6 +4569,7 @@ int cnss_auto_resume(struct device *dev)
 	mutex_unlock(&pci_priv->bus_lock);
 
 	cnss_request_bus_bandwidth(dev, plat_priv->icc.current_bw_vote);
+	pci_priv->drv_connected_last = 0;
 
 	return 0;
 }
@@ -5079,6 +5077,9 @@ int cnss_pci_load_tme_opt_file(struct cnss_pci_data *pci_priv,
 		return 0;
 	}
 
+	if (!tme_lite_mem)
+		return 0;
+
 	if (!tme_lite_mem->va && !tme_lite_mem->size) {
 		cnss_pci_add_fw_prefix_name(pci_priv, filename,
 					    tme_opt_filename);

cnss2/qmi.c

@@ -1023,7 +1023,8 @@ int cnss_wlfw_tme_opt_file_dnld_send_sync(struct cnss_plat_data *plat_priv,
 		file_name = TME_DPR_FILE_NAME;
 	}
 
-	if (!tme_opt_file_mem->pa || !tme_opt_file_mem->size) {
+	if (!tme_opt_file_mem || !tme_opt_file_mem->pa ||
+	    !tme_opt_file_mem->size) {
 		cnss_pr_err("Memory for TME opt file is not available\n");
 		ret = -ENOMEM;
 		goto out;

cnss_utils/Kconfig

@@ -23,3 +23,8 @@ config CNSS_OUT_OF_TREE
 	bool "Build module out-of-tree"
 	help
 	  This enables building the module out of the main kernel tree
+
+config FEATURE_SMEM_MAILBOX
+	bool "Enable Feature SMEM Mailbox"
+	default n
+

cnss_utils/cnss_utils.c

@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2017, 2019, 2021 The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2017, 2019, 2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #define pr_fmt(fmt) "cnss_utils: " fmt
 
@@ -15,6 +18,10 @@
 #include <net/cnss_utils.h>
 #endif
 
+#ifdef CONFIG_FEATURE_SMEM_MAILBOX
+#include <smem-mailbox.h>
+#endif
+
 #define CNSS_MAX_CH_NUM 157
 struct cnss_unsafe_channel_list {
 	u16 unsafe_ch_count;
@@ -53,6 +60,10 @@ static struct cnss_utils_priv {
 	/* generic mutex for device_id */
 	struct mutex cnss_device_id_lock;
 	enum cnss_utils_device_type cnss_device_type;
+#ifdef CONFIG_FEATURE_SMEM_MAILBOX
+	bool smem_mailbox_initialized;
+	int smem_mailbox_id;
+#endif
 } *cnss_utils_priv;
 
 int cnss_utils_set_wlan_unsafe_channel(struct device *dev,
@@ -342,6 +353,27 @@ enum cnss_utils_cc_src cnss_utils_get_cc_source(struct device *dev)
 }
 EXPORT_SYMBOL(cnss_utils_get_cc_source);
 
+#ifdef CONFIG_FEATURE_SMEM_MAILBOX
+int cnss_utils_smem_mailbox_write(struct device *dev, int flags,
+				  const __u8 *data, uint32_t len)
+{
+	struct cnss_utils_priv *priv = cnss_utils_priv;
+
+	if (!priv)
+		return -EINVAL;
+	if (!priv->smem_mailbox_initialized) {
+		if (smem_mailbox_start(priv->smem_mailbox_id, NULL) != 1) {
+			pr_err("Didn't init smem mailbox properly\n");
+			return -EINVAL;
+		} else
+			priv->smem_mailbox_initialized = true;
+	}
+	return smem_mailbox_write(priv->smem_mailbox_id, flags, (__u8 *)data,
+				  len);
+}
+EXPORT_SYMBOL(cnss_utils_smem_mailbox_write);
+#endif
+
 static ssize_t cnss_utils_mac_write(struct file *fp,
 				    const char __user *user_buf,
 				    size_t count, loff_t *off)
@@ -496,6 +528,31 @@ static bool cnss_utils_is_valid_dt_node_found(void)
 	return false;
 }
 
+#ifdef CONFIG_FEATURE_SMEM_MAILBOX
+static void cnss_utils_smem_mailbox_init(void)
+{
+	struct cnss_utils_priv *priv = cnss_utils_priv;
+
+	priv->smem_mailbox_id = 0;
+	priv->smem_mailbox_initialized = false;
+}
+
+static void cnss_utils_smem_mailbox_deinit(void)
+{
+	struct cnss_utils_priv *priv = cnss_utils_priv;
+
+	smem_mailbox_stop(priv->smem_mailbox_id);
+}
+#else
+static void cnss_utils_smem_mailbox_init(void)
+{
+}
+
+static void cnss_utils_smem_mailbox_deinit(void)
+{
+}
+#endif
+
 static int __init cnss_utils_init(void)
 {
 	struct cnss_utils_priv *priv = NULL;
@@ -515,12 +572,13 @@ static int __init cnss_utils_init(void)
 	spin_lock_init(&priv->dfs_nol_info_lock);
 	cnss_utils_debugfs_create(priv);
 	cnss_utils_priv = priv;
-
+	cnss_utils_smem_mailbox_init();
 	return 0;
 }
 
 static void __exit cnss_utils_exit(void)
 {
+	cnss_utils_smem_mailbox_deinit();
 	kfree(cnss_utils_priv);
 	cnss_utils_priv = NULL;
 }

cnss_utils/wlan_firmware_service_v01.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */
-/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+/* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
 
 #include "wlan_firmware_service_v01.h"
 #include <linux/module.h>
@@ -573,7 +573,7 @@ static struct qmi_elem_info wlfw_dev_mem_info_s_v01_ei[] = {
 	},
 };
 
-static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = {
+static struct qmi_elem_info mlo_chip_info_s_v01_ei[] = {
 	{
 		.data_type      = QMI_UNSIGNED_1_BYTE,
 		.elem_len       = 1,
@@ -581,7 +581,7 @@ static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = {
 		.array_type       = NO_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_info_s_v01,
+					   mlo_chip_info_s_v01,
 					   chip_id),
 	},
 	{
@@ -591,7 +591,7 @@ static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = {
 		.array_type       = NO_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_info_s_v01,
+					   mlo_chip_info_s_v01,
 					   num_local_links),
 	},
 	{
@@ -601,7 +601,7 @@ static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = {
 		.array_type       = STATIC_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_info_s_v01,
+					   mlo_chip_info_s_v01,
 					   hw_link_id),
 	},
 	{
@@ -611,7 +611,7 @@ static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = {
 		.array_type       = STATIC_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_info_s_v01,
+					   mlo_chip_info_s_v01,
 					   valid_mlo_link_id),
 	},
 	{
@@ -621,17 +621,17 @@ static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = {
 	},
 };
 
-static struct qmi_elem_info wlfw_host_mlo_chip_v2_info_s_v01_ei[] = {
+static struct qmi_elem_info mlo_chip_v2_info_s_v01_ei[] = {
 	{
 		.data_type      = QMI_STRUCT,
 		.elem_len       = 1,
-		.elem_size      = sizeof(struct wlfw_host_mlo_chip_info_s_v01),
+		.elem_size      = sizeof(struct mlo_chip_info_s_v01),
 		.array_type       = NO_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_v2_info_s_v01,
+					   mlo_chip_v2_info_s_v01,
 					   mlo_chip_info),
-		.ei_array      = wlfw_host_mlo_chip_info_s_v01_ei,
+		.ei_array      = mlo_chip_info_s_v01_ei,
 	},
 	{
 		.data_type      = QMI_UNSIGNED_1_BYTE,
@@ -640,19 +640,19 @@ static struct qmi_elem_info wlfw_host_mlo_chip_v2_info_s_v01_ei[] = {
 		.array_type       = NO_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_v2_info_s_v01,
+					   mlo_chip_v2_info_s_v01,
 					   adj_mlo_num_chips),
 	},
 	{
 		.data_type      = QMI_STRUCT,
-		.elem_len       = QMI_WLFW_MAX_NUM_ADJ_MLO_CHIPS_V01,
-		.elem_size      = sizeof(struct wlfw_host_mlo_chip_info_s_v01),
+		.elem_len       = QMI_WLFW_MAX_ADJ_CHIP_V01,
+		.elem_size      = sizeof(struct mlo_chip_info_s_v01),
 		.array_type       = STATIC_ARRAY,
 		.tlv_type       = 0,
 		.offset         = offsetof(struct
-					   wlfw_host_mlo_chip_v2_info_s_v01,
+					   mlo_chip_v2_info_s_v01,
 					   adj_mlo_chip_info),
-		.ei_array      = wlfw_host_mlo_chip_info_s_v01_ei,
+		.ei_array      = mlo_chip_info_s_v01_ei,
 	},
 	{
 		.data_type      = QMI_EOTI,
@@ -3910,14 +3910,14 @@ struct qmi_elem_info wlfw_host_cap_req_msg_v01_ei[] = {
 	},
 	{
 		.data_type      = QMI_STRUCT,
-		.elem_len       = QMI_WLFW_MAX_NUM_MLO_CHIPS_V01,
-		.elem_size      = sizeof(struct wlfw_host_mlo_chip_info_s_v01),
+		.elem_len       = QMI_WLFW_MAX_MLO_CHIP_V01,
+		.elem_size      = sizeof(struct mlo_chip_info_s_v01),
 		.array_type       = STATIC_ARRAY,
 		.tlv_type       = 0x26,
 		.offset         = offsetof(struct
 					   wlfw_host_cap_req_msg_v01,
 					   mlo_chip_info),
-		.ei_array      = wlfw_host_mlo_chip_info_s_v01_ei,
+		.ei_array      = mlo_chip_info_s_v01_ei,
 	},
 	{
 		.data_type      = QMI_OPT_FLAG,
@@ -4101,14 +4101,14 @@ struct qmi_elem_info wlfw_host_cap_req_msg_v01_ei[] = {
 	},
 	{
 		.data_type      = QMI_STRUCT,
-		.elem_len       = QMI_WLFW_MAX_NUM_MLO_V2_CHIPS_V01,
-		.elem_size      = sizeof(struct wlfw_host_mlo_chip_v2_info_s_v01),
+		.elem_len       = QMI_WLFW_MLO_V2_CHP_V01,
+		.elem_size      = sizeof(struct mlo_chip_v2_info_s_v01),
 		.array_type       = STATIC_ARRAY,
 		.tlv_type       = 0x2F,
 		.offset         = offsetof(struct
 					   wlfw_host_cap_req_msg_v01,
 					   mlo_chip_v2_info),
-		.ei_array      = wlfw_host_mlo_chip_v2_info_s_v01_ei,
+		.ei_array      = mlo_chip_v2_info_s_v01_ei,
 	},
 	{
 		.data_type      = QMI_OPT_FLAG,
@@ -6638,6 +6638,55 @@ struct qmi_elem_info wlfw_tme_lite_info_resp_msg_v01_ei[] = {
 };
 EXPORT_SYMBOL(wlfw_tme_lite_info_resp_msg_v01_ei);
 
+struct qmi_elem_info wlfw_soft_sku_info_req_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_UNSIGNED_8_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u64),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x01,
+		.offset         = offsetof(struct
+					   wlfw_soft_sku_info_req_msg_v01,
+					   addr),
+	},
+	{
+		.data_type      = QMI_UNSIGNED_4_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u32),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x02,
+		.offset         = offsetof(struct
+					   wlfw_soft_sku_info_req_msg_v01,
+					   size),
+	},
+	{
+		.data_type      = QMI_EOTI,
+		.array_type       = NO_ARRAY,
+		.tlv_type       = QMI_COMMON_TLV_TYPE,
+	},
+};
+EXPORT_SYMBOL(wlfw_soft_sku_info_req_msg_v01_ei);
+
+struct qmi_elem_info wlfw_soft_sku_info_resp_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_STRUCT,
+		.elem_len       = 1,
+		.elem_size      = sizeof(struct qmi_response_type_v01),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x02,
+		.offset         = offsetof(struct
+					   wlfw_soft_sku_info_resp_msg_v01,
+					   resp),
+		.ei_array      = qmi_response_type_v01_ei,
+	},
+	{
+		.data_type      = QMI_EOTI,
+		.array_type       = NO_ARRAY,
+		.tlv_type       = QMI_COMMON_TLV_TYPE,
+	},
+};
+EXPORT_SYMBOL(wlfw_soft_sku_info_resp_msg_v01_ei);
+
 struct qmi_elem_info wlfw_fw_ssr_ind_msg_v01_ei[] = {
 	{
 		.data_type      = QMI_SIGNED_4_BYTE_ENUM,
@@ -6735,6 +6784,177 @@ struct qmi_elem_info wlfw_lpass_ssr_resp_msg_v01_ei[] = {
 };
 EXPORT_SYMBOL(wlfw_lpass_ssr_resp_msg_v01_ei);
 
+struct qmi_elem_info wlfw_mlo_reconfig_info_req_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x10,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_capable_valid),
+	},
+	{
+		.data_type      = QMI_UNSIGNED_1_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x10,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_capable),
+	},
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x11,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_chip_id_valid),
+	},
+	{
+		.data_type      = QMI_UNSIGNED_2_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u16),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x11,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_chip_id),
+	},
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x12,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_group_id_valid),
+	},
+	{
+		.data_type      = QMI_UNSIGNED_1_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x12,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_group_id),
+	},
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x13,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   max_mlo_peer_valid),
+	},
+	{
+		.data_type      = QMI_UNSIGNED_2_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u16),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x13,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   max_mlo_peer),
+	},
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x14,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_num_chips_valid),
+	},
+	{
+		.data_type      = QMI_UNSIGNED_1_BYTE,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x14,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_num_chips),
+	},
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x15,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_chip_info_valid),
+	},
+	{
+		.data_type      = QMI_STRUCT,
+		.elem_len       = QMI_WLFW_MAX_MLO_CHIP_V01,
+		.elem_size      = sizeof(struct mlo_chip_info_s_v01),
+		.array_type       = STATIC_ARRAY,
+		.tlv_type       = 0x15,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_chip_info),
+		.ei_array      = mlo_chip_info_s_v01_ei,
+	},
+	{
+		.data_type      = QMI_OPT_FLAG,
+		.elem_len       = 1,
+		.elem_size      = sizeof(u8),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x16,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_chip_v2_info_valid),
+	},
+	{
+		.data_type      = QMI_STRUCT,
+		.elem_len       = QMI_WLFW_MLO_V2_CHP_V01,
+		.elem_size      = sizeof(struct mlo_chip_v2_info_s_v01),
+		.array_type       = STATIC_ARRAY,
+		.tlv_type       = 0x16,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_req_msg_v01,
+					   mlo_chip_v2_info),
+		.ei_array      = mlo_chip_v2_info_s_v01_ei,
+	},
+	{
+		.data_type      = QMI_EOTI,
+		.array_type       = NO_ARRAY,
+		.tlv_type       = QMI_COMMON_TLV_TYPE,
+	},
+};
+EXPORT_SYMBOL(wlfw_mlo_reconfig_info_req_msg_v01_ei);
+
+struct qmi_elem_info wlfw_mlo_reconfig_info_resp_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_STRUCT,
+		.elem_len       = 1,
+		.elem_size      = sizeof(struct qmi_response_type_v01),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x02,
+		.offset         = offsetof(struct
+					   wlfw_mlo_reconfig_info_resp_msg_v01,
+					   resp),
+		.ei_array      = qmi_response_type_v01_ei,
+	},
+	{
+		.data_type      = QMI_EOTI,
+		.array_type       = NO_ARRAY,
+		.tlv_type       = QMI_COMMON_TLV_TYPE,
+	},
+};
+EXPORT_SYMBOL(wlfw_mlo_reconfig_info_resp_msg_v01_ei);
+
 /**
  * wlfw_is_valid_dt_node_found - Check if valid device tree node present
  *
@@ -6767,6 +6987,5 @@ static int __init wlfw_init(void)
 }
 
 module_init(wlfw_init);
-
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("WLAN FW QMI service");

cnss_utils/wlan_firmware_service_v01.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */
-/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+/* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
 
 #ifndef WLAN_FIRMWARE_SERVICE_V01_H
 #define WLAN_FIRMWARE_SERVICE_V01_H
@@ -26,6 +26,7 @@
 #define QMI_WLFW_QDSS_TRACE_MODE_RESP_V01 0x0045
 #define QMI_WLFW_AUX_UC_INFO_REQ_V01 0x005A
 #define QMI_WLFW_FW_READY_IND_V01 0x0021
+#define QMI_WLFW_SOFT_SKU_INFO_RESP_V01 0x0060
 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_RESP_V01 0x0040
 #define QMI_WLFW_CAL_UPDATE_REQ_V01 0x0029
 #define QMI_WLFW_PHY_CAP_REQ_V01 0x0057
@@ -64,6 +65,7 @@
 #define QMI_WLFW_PCIE_LINK_CTRL_REQ_V01 0x0059
 #define QMI_WLFW_MAC_ADDR_REQ_V01 0x0033
 #define QMI_WLFW_WLAN_CFG_REQ_V01 0x0023
+#define QMI_WLFW_MLO_RECONFIG_INFO_REQ_V01 0x005F
 #define QMI_WLFW_ANTENNA_GRANT_REQ_V01 0x0048
 #define QMI_WLFW_BDF_DOWNLOAD_REQ_V01 0x0025
 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037
@@ -71,6 +73,7 @@
 #define QMI_WLFW_RESPOND_GET_INFO_IND_V01 0x004B
 #define QMI_WLFW_QDSS_TRACE_DATA_REQ_V01 0x0042
 #define QMI_WLFW_LPASS_SSR_REQ_V01 0x005E
+#define QMI_WLFW_MLO_RECONFIG_INFO_RESP_V01 0x005F
 #define QMI_WLFW_CAL_DOWNLOAD_RESP_V01 0x0027
 #define QMI_WLFW_INI_RESP_V01 0x002F
 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01 0x0040
@@ -98,6 +101,7 @@
 #define QMI_WLFW_HOST_CAP_REQ_V01 0x0034
 #define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01 0x0044
 #define QMI_WLFW_GET_INFO_REQ_V01 0x004A
+#define QMI_WLFW_SOFT_SKU_INFO_REQ_V01 0x0060
 #define QMI_WLFW_CAL_DONE_IND_V01 0x003E
 #define QMI_WLFW_M3_DUMP_UPLOAD_REQ_IND_V01 0x004D
 #define QMI_WLFW_WFC_CALL_STATUS_RESP_V01 0x0049
@@ -120,17 +124,17 @@
 #define QMI_WLFW_MAX_NUM_CAL_V01 5
 #define QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01 64
 #define QMI_WLFW_MAX_HOST_DDR_RANGE_SIZE_V01 3
-#define QMI_WLFW_MAX_NUM_ADJ_MLO_CHIPS_V01 2
+#define QMI_WLFW_MAX_MLO_CHIP_V01 3
 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V01 24
 #define QMI_WLFW_MAX_BUILD_ID_LEN_V01 128
 #define QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
-#define QMI_WLFW_MAX_NUM_MLO_V2_CHIPS_V01 4
 #define QMI_WLFW_MAX_NUM_SHARE_MEM_V01 8
 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
 #define QMI_WLFW_MAX_NUM_SVC_V01 24
 #define QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01 2
 #define QMI_WLFW_MAC_ADDR_SIZE_V01 6
 #define QMI_WLFW_MAX_NUM_GPIO_INFO_V01 20
+#define QMI_WLFW_MLO_V2_CHP_V01 4
 #define QMI_WLFW_MAX_NUM_MEM_CFG_V01 2
 #define QMI_WLFW_PMU_PARAMS_MAX_V01 16
 #define QMI_WLFW_MAX_NUM_MEM_SEG_V01 52
@@ -144,10 +148,10 @@
 #define QMI_WLFW_MAX_STR_LEN_V01 16
 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V3_V01 60
 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01 36
+#define QMI_WLFW_MAX_ADJ_CHIP_V01 2
 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 40
 #define QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01 6144
 #define QMI_WLFW_MAX_NUM_GPIO_V01 32
-#define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
 
 enum wlfw_driver_mode_enum_v01 {
 	WLFW_DRIVER_MODE_ENUM_MIN_VAL_V01 = INT_MIN,
@@ -402,7 +406,7 @@ enum wlfw_lpass_ssr_reason_v01 {
 #define QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01 ((u64)0x01ULL)
 #define QMI_WLFW_DIRECT_LINK_SUPPORT_V01 ((u64)0x02ULL)
 #define QMI_WLFW_AUX_UC_SUPPORT_V01 ((u64)0x04ULL)
-#define QMI_WLFW_CALDB_SEG_DDR_SUPPORT_V01 ((u64)0x08ull)
+#define QMI_WLFW_CALDB_SEG_DDR_SUPPORT_V01 ((u64)0x08ULL)
 
 struct wlfw_ce_tgt_pipe_cfg_s_v01 {
 	u32 pipe_num;
@@ -498,17 +502,17 @@ struct wlfw_dev_mem_info_s_v01 {
 	u64 size;
 };
 
-struct wlfw_host_mlo_chip_info_s_v01 {
+struct mlo_chip_info_s_v01 {
 	u8 chip_id;
 	u8 num_local_links;
 	u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
 	u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
 };
 
-struct wlfw_host_mlo_chip_v2_info_s_v01 {
-	struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info;
+struct mlo_chip_v2_info_s_v01 {
+	struct mlo_chip_info_s_v01 mlo_chip_info;
 	u8 adj_mlo_num_chips;
-	struct wlfw_host_mlo_chip_info_s_v01 adj_mlo_chip_info[QMI_WLFW_MAX_NUM_ADJ_MLO_CHIPS_V01];
+	struct mlo_chip_info_s_v01 adj_mlo_chip_info[QMI_WLFW_MAX_ADJ_CHIP_V01];
 };
 
 struct wlfw_pmu_param_v01 {
@@ -991,7 +995,7 @@ struct wlfw_host_cap_req_msg_v01 {
 	u8 mlo_num_chips_valid;
 	u8 mlo_num_chips;
 	u8 mlo_chip_info_valid;
-	struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
+	struct mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_MLO_CHIP_V01];
 	u8 feature_list_valid;
 	u64 feature_list;
 	u8 num_wlan_clients_valid;
@@ -1010,7 +1014,7 @@ struct wlfw_host_cap_req_msg_v01 {
 	u8 fw_ini_cfg_support_valid;
 	u8 fw_ini_cfg_support;
 	u8 mlo_chip_v2_info_valid;
-	struct wlfw_host_mlo_chip_v2_info_s_v01 mlo_chip_v2_info[QMI_WLFW_MAX_NUM_MLO_V2_CHIPS_V01];
+	struct mlo_chip_v2_info_s_v01 mlo_chip_v2_info[QMI_WLFW_MLO_V2_CHP_V01];
 	u8 pcie_link_info_valid;
 	struct wlfw_host_pcie_link_info_s_v01 pcie_link_info;
 };
@@ -1536,6 +1540,19 @@ struct wlfw_tme_lite_info_resp_msg_v01 {
 #define WLFW_TME_LITE_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
 extern struct qmi_elem_info wlfw_tme_lite_info_resp_msg_v01_ei[];
 
+struct wlfw_soft_sku_info_req_msg_v01 {
+	u64 addr;
+	u32 size;
+};
+#define WLFW_SOFT_SKU_INFO_REQ_MSG_V01_MAX_MSG_LEN 18
+extern struct qmi_elem_info wlfw_soft_sku_info_req_msg_v01_ei[];
+
+struct wlfw_soft_sku_info_resp_msg_v01 {
+	struct qmi_response_type_v01 resp;
+};
+#define WLFW_SOFT_SKU_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
+extern struct qmi_elem_info wlfw_soft_sku_info_resp_msg_v01_ei[];
+
 struct wlfw_fw_ssr_ind_msg_v01 {
 	enum wlfw_fw_ssr_reason_v01 reason_code;
 };
@@ -1566,4 +1583,29 @@ struct wlfw_lpass_ssr_resp_msg_v01 {
 #define WLFW_LPASS_SSR_RESP_MSG_V01_MAX_MSG_LEN 7
 extern struct qmi_elem_info wlfw_lpass_ssr_resp_msg_v01_ei[];
 
+struct wlfw_mlo_reconfig_info_req_msg_v01 {
+	u8 mlo_capable_valid;
+	u8 mlo_capable;
+	u8 mlo_chip_id_valid;
+	u16 mlo_chip_id;
+	u8 mlo_group_id_valid;
+	u8 mlo_group_id;
+	u8 max_mlo_peer_valid;
+	u16 max_mlo_peer;
+	u8 mlo_num_chips_valid;
+	u8 mlo_num_chips;
+	u8 mlo_chip_info_valid;
+	struct mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_MLO_CHIP_V01];
+	u8 mlo_chip_v2_info_valid;
+	struct mlo_chip_v2_info_s_v01 mlo_chip_v2_info[QMI_WLFW_MLO_V2_CHP_V01];
+};
+#define WLFW_MLO_RECONFIG_INFO_REQ_MSG_V01_MAX_MSG_LEN 122
+extern struct qmi_elem_info wlfw_mlo_reconfig_info_req_msg_v01_ei[];
+
+struct wlfw_mlo_reconfig_info_resp_msg_v01 {
+	struct qmi_response_type_v01 resp;
+};
+#define WLFW_MLO_RECONFIG_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
+extern struct qmi_elem_info wlfw_mlo_reconfig_info_resp_msg_v01_ei[];
+
 #endif

icnss2/Kconfig

@@ -51,3 +51,10 @@ config WCNSS_MEM_PRE_ALLOC
 	  This feature enable cld wlan driver to use pre allocated memory
 	  for it's internal usage and release it to back to pre allocated pool.
 	  This memory is allocated at the cold boot time.
+
+config SLATE_MODULE_ENABLED
+	bool "Enable Slate usage"
+	depends on ICNSS2
+	help
+	  Enable slate compilation.
+	  This config enables slate code for compilation.

icnss2/main.c

@@ -45,10 +45,8 @@
 #include <linux/soc/qcom/pdr.h>
 #include <linux/remoteproc.h>
 #include <linux/version.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
 #include <trace/hooks/remoteproc.h>
-#endif
-#ifdef SLATE_MODULE_ENABLED
+#ifdef CONFIG_SLATE_MODULE_ENABLED
 #include <linux/soc/qcom/slatecom_interface.h>
 #include <linux/soc/qcom/slate_events_bridge_intf.h>
 #include <uapi/linux/slatecom_interface.h>
@@ -481,7 +479,7 @@ static int icnss_send_smp2p(struct icnss_priv *priv,
 	unsigned int value = 0;
 	int ret;
 
-	if (!priv || IS_ERR(priv->smp2p_info[smp2p_entry].smem_state))
+	if (!priv || IS_ERR_OR_NULL(priv->smp2p_info[smp2p_entry].smem_state))
 		return -EINVAL;
 
 	/* No Need to check FW_DOWN for ICNSS_RESET_MSG */
@@ -681,7 +679,7 @@ static int icnss_get_temperature(struct icnss_priv *priv, int *temp)
 
 	icnss_pr_dbg("Thermal Sensor is %s\n", tsens);
 	thermal_dev = thermal_zone_get_zone_by_name(tsens);
-	if (IS_ERR(thermal_dev)) {
+	if (IS_ERR_OR_NULL(thermal_dev)) {
 		icnss_pr_err("Fail to get thermal zone. ret: %d",
 			     PTR_ERR(thermal_dev));
 		return PTR_ERR(thermal_dev);
@@ -812,7 +810,7 @@ retry:
 		qcom_smem_state_get(&priv->pdev->dev,
 				    icnss_smp2p_str[smp2p_entry],
 				    &priv->smp2p_info[smp2p_entry].smem_bit);
-	if (IS_ERR(priv->smp2p_info[smp2p_entry].smem_state)) {
+	if (IS_ERR_OR_NULL(priv->smp2p_info[smp2p_entry].smem_state)) {
 		if (retry++ < SMP2P_GET_MAX_RETRY) {
 			error = PTR_ERR(priv->smp2p_info[smp2p_entry].smem_state);
 			icnss_pr_err("Failed to get smem state, ret: %d Entry: %s",
@@ -849,7 +847,7 @@ static enum wlfw_wlan_rf_subtype_v01 icnss_rf_subtype_value_to_type(u32 val)
 	}
 }
 
-#ifdef SLATE_MODULE_ENABLED
+#ifdef CONFIG_SLATE_MODULE_ENABLED
 static void icnss_send_wlan_boot_init(void)
 {
 	send_wlan_state(GMI_MGR_WLAN_BOOT_INIT);
@@ -2365,7 +2363,7 @@ static int icnss_wpss_early_ssr_register_notifier(struct icnss_priv *priv)
 		qcom_register_early_ssr_notifier("wpss",
 						 &priv->wpss_early_ssr_nb);
 
-	if (IS_ERR(priv->wpss_early_notify_handler)) {
+	if (IS_ERR_OR_NULL(priv->wpss_early_notify_handler)) {
 		ret = PTR_ERR(priv->wpss_early_notify_handler);
 		icnss_pr_err("WPSS register early notifier failed: %d\n", ret);
 	}
@@ -2387,7 +2385,7 @@ static int icnss_wpss_ssr_register_notifier(struct icnss_priv *priv)
 	priv->wpss_notify_handler =
 		qcom_register_ssr_notifier("wpss", &priv->wpss_ssr_nb);
 
-	if (IS_ERR(priv->wpss_notify_handler)) {
+	if (IS_ERR_OR_NULL(priv->wpss_notify_handler)) {
 		ret = PTR_ERR(priv->wpss_notify_handler);
 		icnss_pr_err("WPSS register notifier failed: %d\n", ret);
 	}
@@ -2397,7 +2395,7 @@ static int icnss_wpss_ssr_register_notifier(struct icnss_priv *priv)
 	return ret;
 }
 
-#ifdef SLATE_MODULE_ENABLED
+#ifdef CONFIG_SLATE_MODULE_ENABLED
 static int icnss_slate_event_notifier_nb(struct notifier_block *nb,
 					 unsigned long event, void *data)
 {
@@ -2495,7 +2493,7 @@ static int icnss_slate_ssr_register_notifier(struct icnss_priv *priv)
 	priv->slate_notify_handler =
 		qcom_register_ssr_notifier("slatefw", &priv->slate_ssr_nb);
 
-	if (IS_ERR(priv->slate_notify_handler)) {
+	if (IS_ERR_OR_NULL(priv->slate_notify_handler)) {
 		ret = PTR_ERR(priv->slate_notify_handler);
 		icnss_pr_err("SLATE register notifier failed: %d\n", ret);
 	}
@@ -2552,7 +2550,7 @@ static int icnss_modem_ssr_register_notifier(struct icnss_priv *priv)
 	priv->modem_notify_handler =
 		qcom_register_ssr_notifier("mpss", &priv->modem_ssr_nb);
 
-	if (IS_ERR(priv->modem_notify_handler)) {
+	if (IS_ERR_OR_NULL(priv->modem_notify_handler)) {
 		ret = PTR_ERR(priv->modem_notify_handler);
 		icnss_pr_err("Modem register notifier failed: %d\n", ret);
 	}
@@ -2564,7 +2562,7 @@ static int icnss_modem_ssr_register_notifier(struct icnss_priv *priv)
 
 static void icnss_wpss_early_ssr_unregister_notifier(struct icnss_priv *priv)
 {
-	if (IS_ERR(priv->wpss_early_notify_handler))
+	if (IS_ERR_OR_NULL(priv->wpss_early_notify_handler))
 		return;
 
 	qcom_unregister_early_ssr_notifier(priv->wpss_early_notify_handler,
@@ -4693,7 +4691,6 @@ static inline bool icnss_use_nv_mac(struct icnss_priv *priv)
 				     "use-nv-mac");
 }
 
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
 static void rproc_restart_level_notifier(void *data, struct rproc *rproc)
 {
 	struct icnss_subsys_restart_level_data *restart_level_data;
@@ -4715,7 +4712,6 @@ static void rproc_restart_level_notifier(void *data, struct rproc *rproc)
 					0, restart_level_data);
 	}
 }
-#endif
 
 #if IS_ENABLED(CONFIG_WCNSS_MEM_PRE_ALLOC)
 static void icnss_initialize_mem_pool(unsigned long device_id)
@@ -4735,31 +4731,15 @@ static void icnss_deinitialize_mem_pool(void)
 }
 #endif
 
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
 static void register_rproc_restart_level_notifier(void)
 {
 	register_trace_android_vh_rproc_recovery_set(rproc_restart_level_notifier, NULL);
 }
-#else
-static void register_rproc_restart_level_notifier(void)
-{
-	return;
-}
-#endif
 
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
 static void unregister_rproc_restart_level_notifier(void)
 {
 	unregister_trace_android_vh_rproc_recovery_set(rproc_restart_level_notifier, NULL);
 }
-#else
-static void unregister_rproc_restart_level_notifier(void)
-{
-	return;
-}
-#endif
-
-
 
 static int icnss_probe(struct platform_device *pdev)
 {
@@ -5062,7 +5042,7 @@ static int icnss_pm_suspend(struct device *dev)
 	icnss_pr_vdbg("PM Suspend, state: 0x%lx\n", priv->state);
 
 	if (!priv->ops || !priv->ops->pm_suspend ||
-	    IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state) ||
+	    IS_ERR_OR_NULL(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state) ||
 	    !test_bit(ICNSS_DRIVER_PROBED, &priv->state))
 		return 0;
 
@@ -5100,7 +5080,7 @@ static int icnss_pm_resume(struct device *dev)
 	icnss_pr_vdbg("PM resume, state: 0x%lx\n", priv->state);
 
 	if (!priv->ops || !priv->ops->pm_resume ||
-	    IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state) ||
+	    IS_ERR_OR_NULL(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state) ||
 	    !test_bit(ICNSS_DRIVER_PROBED, &priv->state))
 		goto out;
 
@@ -5191,7 +5171,7 @@ static int icnss_pm_runtime_suspend(struct device *dev)
 	}
 
 	if (!priv->ops || !priv->ops->runtime_suspend ||
-	    IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state))
+	    IS_ERR_OR_NULL(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state))
 		goto out;
 
 	icnss_pr_vdbg("Runtime suspend\n");
@@ -5225,7 +5205,7 @@ static int icnss_pm_runtime_resume(struct device *dev)
 	}
 
 	if (!priv->ops || !priv->ops->runtime_resume ||
-	    IS_ERR(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state))
+	    IS_ERR_OR_NULL(priv->smp2p_info[ICNSS_SMP2P_OUT_POWER_SAVE].smem_state))
 		goto out;
 
 	icnss_pr_vdbg("Runtime resume, state: 0x%lx\n", priv->state);

icnss2/main.h

@@ -519,7 +519,7 @@ struct icnss_priv {
 	u32 rf_subtype;
 	u8 is_slate_rfa;
 	struct completion slate_boot_complete;
-#ifdef SLATE_MODULE_ENABLED
+#ifdef CONFIG_SLATE_MODULE_ENABLED
 	struct seb_notif_info *seb_handle;
 	struct notifier_block seb_nb;
 #endif

icnss2/monaco_consolidate_defconfig

@@ -4,3 +4,4 @@ CONFIG_ICNSS2_QMI=y
 CONFIG_CNSS_QMI_SVC=m
 CONFIG_CNSS_OUT_OF_TREE=y
 CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_SLATE_MODULE_ENABLED=y

icnss2/monaco_gki_defconfig

@@ -3,3 +3,4 @@ CONFIG_ICNSS2_QMI=y
 CONFIG_CNSS_QMI_SVC=m
 CONFIG_CNSS_OUT_OF_TREE=y
 CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_SLATE_MODULE_ENABLED=y

icnss2/qmi.c

@@ -3509,6 +3509,7 @@ int icnss_wlfw_get_info_send_sync(struct icnss_priv *plat_priv, int type,
 	struct wlfw_get_info_resp_msg_v01 *resp;
 	struct qmi_txn txn;
 	int ret = 0;
+	int flags = GFP_KERNEL & ~__GFP_DIRECT_RECLAIM;
 
 	if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
 		return -EINVAL;
@@ -3516,11 +3517,11 @@ int icnss_wlfw_get_info_send_sync(struct icnss_priv *plat_priv, int type,
 	if (test_bit(ICNSS_FW_DOWN, &plat_priv->state))
 		return -EINVAL;
 
-	req = kzalloc(sizeof(*req), GFP_KERNEL);
+	req = kzalloc(sizeof(*req), flags);
 	if (!req)
 		return -ENOMEM;
 
-	resp = kzalloc(sizeof(*resp), GFP_KERNEL);
+	resp = kzalloc(sizeof(*resp), flags);
 	if (!resp) {
 		kfree(req);
 		return -ENOMEM;

inc/cnss2.h

@@ -436,6 +436,7 @@ extern int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg);
 extern int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
 				     struct cnss_mem_segment segment[],
 				     u32 segment_count);
+extern bool cnss_get_audio_shared_iommu_group_cap(struct device *dev);
 extern int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
 			       dma_addr_t iova, size_t size);
 extern void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova,

inc/cnss_utils.h

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #ifndef _CNSS_UTILS_H_
 #define _CNSS_UTILS_H_
@@ -44,4 +47,9 @@ extern void cnss_utils_set_cc_source(struct device *dev,
 				     enum cnss_utils_cc_src cc_source);
 extern enum cnss_utils_cc_src cnss_utils_get_cc_source(struct device *dev);
 
+#ifdef CONFIG_FEATURE_SMEM_MAILBOX
+extern int cnss_utils_smem_mailbox_write(struct device *dev, int flags,
+					 const __u8 *data, uint32_t len);
+#endif
+
 #endif