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Merge "video: driver: refine power settings"

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This commit is contained in:
qctecmdr
2021-04-27 20:34:02 -07:00
committed by Gerrit - the friendly Code Review server
parent e1a2a69904 e0637a30b8
commit b85c9199af
2 changed files with 54 additions and 54 deletions
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18
driver/variant/iris2/src/msm_vidc_power_iris2.c
View File

@@ -52,13 +52,13 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
* Even though, most part is common now, in future it may change
* between them.
*/
fw_cycles = fps * core->capabilities[MB_CYCLES_FW].value;
fw_vpp_cycles = fps * core->capabilities[MB_CYCLES_FW_VPP].value;
fw_cycles = fps * inst->capabilities->cap[MB_CYCLES_FW].value;
fw_vpp_cycles = fps * inst->capabilities->cap[MB_CYCLES_FW_VPP].value;
if (inst->domain == MSM_VIDC_ENCODER) {
vpp_cycles_per_mb = is_low_power_session(inst) ?
core->capabilities[MB_CYCLES_LP].value :
core->capabilities[MB_CYCLES_VPP].value;
inst->capabilities->cap[MB_CYCLES_LP].value :
inst->capabilities->cap[MB_CYCLES_VPP].value;
vpp_cycles = mbs_per_second * vpp_cycles_per_mb /
inst->capabilities->cap[PIPE].value;
@@ -90,7 +90,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
vsp_cycles = div_u64(((u64)inst->capabilities->cap[BIT_RATE].value *
vsp_factor_num), vsp_factor_den);
base_cycles = core->capabilities[MB_CYCLES_VSP].value;
base_cycles = inst->capabilities->cap[MB_CYCLES_VSP].value;
if (inst->codec == MSM_VIDC_VP9) {
vsp_cycles = div_u64(vsp_cycles * 170, 100);
} else if (inst->capabilities->cap[ENTROPY_MODE].value ==
@@ -110,7 +110,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
} else if (inst->domain == MSM_VIDC_DECODER) {
/* VPP */
vpp_cycles = mbs_per_second * core->capabilities[MB_CYCLES_VPP].value /
vpp_cycles = mbs_per_second * inst->capabilities->cap[MB_CYCLES_VPP].value /
inst->capabilities->cap[PIPE].value;
/* 21 / 20 is minimum overhead factor */
vpp_cycles += max(vpp_cycles / 20, fw_vpp_cycles);
@@ -119,7 +119,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
vpp_cycles += div_u64(vpp_cycles * 59, 1000);
/* VSP */
base_cycles = core->capabilities[MB_CYCLES_VSP].value;
base_cycles = inst->capabilities->cap[MB_CYCLES_VSP].value;
vsp_cycles = fps * data_size * 8;
if (inst->codec == MSM_VIDC_VP9) {
@@ -147,8 +147,8 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
freq = max(vpp_cycles, vsp_cycles);
freq = max(freq, fw_cycles);
i_vpr_p(inst, "%s: inst %pK: filled len %d required freq %llu\n",
__func__, inst, data_size, freq);
i_vpr_p(inst, "%s: filled len %d required freq %llu\n",
__func__, data_size, freq);
return freq;
}

90
driver/vidc/src/msm_vidc_driver.c
View File

@@ -2526,16 +2526,58 @@ exit:
return allow;
}
static void msm_vidc_update_input_cr(struct msm_vidc_inst *inst, u32 idx, u32 cr)
{
struct msm_vidc_input_cr_data *temp, *next;
bool found = false;
list_for_each_entry_safe(temp, next, &inst->enc_input_crs, list) {
if (temp->index == idx) {
temp->input_cr = cr;
found = true;
break;
}
}
if (!found) {
temp = kzalloc(sizeof(*temp), GFP_KERNEL);
if (!temp) {
i_vpr_e(inst, "%s: malloc failure.\n", __func__);
return;
}
temp->index = idx;
temp->input_cr = cr;
list_add_tail(&temp->list, &inst->enc_input_crs);
}
}
static void msm_vidc_free_input_cr_list(struct msm_vidc_inst *inst)
{
struct msm_vidc_input_cr_data *temp, *next;
list_for_each_entry_safe(temp, next, &inst->enc_input_crs, list) {
list_del(&temp->list);
kfree(temp);
}
INIT_LIST_HEAD(&inst->enc_input_crs);
}
static int msm_vidc_queue_buffer(struct msm_vidc_inst *inst, struct msm_vidc_buffer *buf)
{
struct msm_vidc_buffer *meta;
int rc = 0;
u32 cr = 0;
if (!inst || !buf || !inst->capabilities) {
d_vpr_e("%s: invalid params\n", __func__);
return -EINVAL;
}
if (is_encode_session(inst) && is_input_buffer(buf->type)) {
cr = inst->capabilities->cap[ENC_IP_CR].value;
msm_vidc_update_input_cr(inst, buf->index, cr);
msm_vidc_update_cap_value(inst, ENC_IP_CR, 0, __func__);
}
if (is_decode_session(inst) && is_input_buffer(buf->type) &&
inst->capabilities->cap[CODEC_CONFIG].value) {
buf->flags |= MSM_VIDC_BUF_FLAG_CODECCONFIG;
@@ -2572,6 +2614,9 @@ static int msm_vidc_queue_buffer(struct msm_vidc_inst *inst, struct msm_vidc_buf
meta->attr |= MSM_VIDC_ATTR_QUEUED;
}
if (is_input_buffer(buf->type))
inst->power.buffer_counter++;
if (buf->type == MSM_VIDC_BUF_INPUT)
msm_vidc_debugfs_update(inst, MSM_VIDC_DEBUGFS_EVENT_ETB);
else if (buf->type == MSM_VIDC_BUF_OUTPUT)
@@ -2608,47 +2653,11 @@ int msm_vidc_queue_buffer_batch(struct msm_vidc_inst *inst)
return 0;
}
void msm_vidc_update_input_cr(struct msm_vidc_inst *inst, u32 idx, u32 cr)
{
struct msm_vidc_input_cr_data *temp, *next;
bool found = false;
list_for_each_entry_safe(temp, next, &inst->enc_input_crs, list) {
if (temp->index == idx) {
temp->input_cr = cr;
found = true;
break;
}
}
if (!found) {
temp = kzalloc(sizeof(*temp), GFP_KERNEL);
if (!temp) {
i_vpr_e(inst, "%s: malloc failure.\n", __func__);
return;
}
temp->index = idx;
temp->input_cr = cr;
list_add_tail(&temp->list, &inst->enc_input_crs);
}
}
void msm_vidc_free_input_cr_list(struct msm_vidc_inst *inst)
{
struct msm_vidc_input_cr_data *temp, *next;
list_for_each_entry_safe(temp, next, &inst->enc_input_crs, list) {
list_del(&temp->list);
kfree(temp);
}
INIT_LIST_HEAD(&inst->enc_input_crs);
}
int msm_vidc_queue_buffer_single(struct msm_vidc_inst *inst, struct vb2_buffer *vb2)
{
int rc = 0;
struct msm_vidc_buffer *buf;
enum msm_vidc_allow allow;
u32 cr = 0;
if (!inst || !vb2) {
d_vpr_e("%s: invalid params\n", __func__);
@@ -2668,15 +2677,6 @@ int msm_vidc_queue_buffer_single(struct msm_vidc_inst *inst, struct vb2_buffer *
return 0;
}
if (buf->type == MSM_VIDC_BUF_INPUT) {
if (is_encode_session(inst)) {
cr = inst->capabilities->cap[ENC_IP_CR].value;
msm_vidc_update_input_cr(inst, vb2->index, cr);
msm_vidc_update_cap_value(inst, ENC_IP_CR, 0, __func__);
}
inst->power.buffer_counter++;
}
msm_vidc_scale_power(inst, is_input_buffer(buf->type));
rc = msm_vidc_queue_buffer(inst, buf);