msm: ipa: Load IPA_CFG offset from DTS

Load the IPA_CFG offset from the DTS and use it for reg_base
offset.

Change-Id: Ib04349b5f35e8b3b4f5cfdf8eee50eabd886484f
Acked-by: Nadav Levintov <[email protected]>
Signed-off-by: Sivan Reinstein <[email protected]>

drivers/platform/msm/ipa/ipa_v3/ipa.c

@@ -6235,7 +6235,7 @@ static int ipa3_post_init(const struct ipa3_plat_drv_res *resource_p,
 	ipa_save_gsi_ver();
 
 	if (ipahal_init(ipa3_ctx->ipa_hw_type, ipa3_ctx->mmio,
-		ipa3_ctx->pdev)) {
+		ipa3_ctx->ipa_cfg_offset, ipa3_ctx->pdev)) {
 		IPAERR("fail to init ipahal\n");
 		result = -EFAULT;
 		goto fail_ipahal;
@@ -7044,6 +7044,7 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
 
 	ipa3_ctx->ipa_wrapper_base = resource_p->ipa_mem_base;
 	ipa3_ctx->ipa_wrapper_size = resource_p->ipa_mem_size;
+	ipa3_ctx->ipa_cfg_offset = resource_p->ipa_cfg_offset;
 	ipa3_ctx->ipa_hw_type = resource_p->ipa_hw_type;
 	ipa3_ctx->ipa_config_is_mhi = resource_p->ipa_mhi_dynamic_config;
 	ipa3_ctx->hw_type_index = ipa3_get_hw_type_index();
@@ -7201,7 +7202,7 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
 		goto fail_mem_ctrl;
 	}
 	result = ipa3_controller_static_bind(ipa3_ctx->ctrl,
-			ipa3_ctx->ipa_hw_type);
+			ipa3_ctx->ipa_hw_type, ipa3_ctx->ipa_cfg_offset);
 	if (result) {
 		IPAERR("fail to static bind IPA ctrl\n");
 		result = -EFAULT;
@@ -8128,7 +8129,18 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
 		IPADBG("uC IPA FW name = %s\n", ipa_drv_res->uc_fw_file_name);
 	else
 		IPADBG("uC IPA FW file not defined. Using default one\n");
+
 	/* Get IPA wrapper address */
+	result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-cfg-offset",
+		&ipa_drv_res->ipa_cfg_offset);
+	if (!result) {
+		IPADBG(": Read offset of IPA_CFG from IPA_WRAPPER_BASE = 0x%x\n",
+			ipa_drv_res->ipa_cfg_offset);
+	} else {
+		ipa_drv_res->ipa_cfg_offset = 0;
+		IPADBG("IPA_CFG_OFFSET not defined. Using default one\n");
+	}
+
 	resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 			"ipa-base");
 	if (!resource) {

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

@@ -1844,6 +1844,7 @@ struct ipa3_app_clock_vote {
  * @mmio: iomem
  * @ipa_wrapper_base: IPA wrapper base address
  * @ipa_wrapper_size: size of the memory pointed to by ipa_wrapper_base
+ * @ipa_cfg_offset: offset from IPA_WRAPPER_BASE to IPA registers
  * @hdr_tbl: IPA header table
  * @hdr_proc_ctx_tbl: IPA processing context table
  * @rt_tbl_set: list of routing tables each of which is a list of rules
@@ -1948,6 +1949,7 @@ struct ipa3_context {
 	void __iomem *mmio;
 	u32 ipa_wrapper_base;
 	u32 ipa_wrapper_size;
+	u32 ipa_cfg_offset;
 	struct ipa3_hdr_tbl hdr_tbl;
 	struct ipa3_hdr_proc_ctx_tbl hdr_proc_ctx_tbl;
 	struct ipa3_rt_tbl_set rt_tbl_set[IPA_IP_MAX];
@@ -2131,6 +2133,7 @@ struct ipa3_plat_drv_res {
 	u32 ipa_mem_size;
 	u32 transport_mem_base;
 	u32 transport_mem_size;
+	u32 ipa_cfg_offset;
 	u32 emulator_intcntrlr_mem_base;
 	u32 emulator_intcntrlr_mem_size;
 	u32 emulator_irq;
@@ -2813,7 +2816,7 @@ void ipa3_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size);
 #endif
 int ipa3_init_mem_partition(enum ipa_hw_type ipa_hw_type);
 int ipa3_controller_static_bind(struct ipa3_controller *controller,
-		enum ipa_hw_type ipa_hw_type);
+		enum ipa_hw_type ipa_hw_type, u32 ipa_cfg_offset);
 int ipa3_cfg_route(struct ipahal_reg_route *route);
 int ipa3_send_cmd_timeout(u16 num_desc, struct ipa3_desc *descr, u32 timeout);
 int ipa3_send_cmd(u16 num_desc, struct ipa3_desc *descr);

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

@@ -7431,7 +7431,7 @@ int ipa3_init_mem_partition(enum ipa_hw_type type)
  *  struct initialization - hard decision... time.vs.mem
  */
 int ipa3_controller_static_bind(struct ipa3_controller *ctrl,
-		enum ipa_hw_type hw_type)
+		enum ipa_hw_type hw_type, u32 ipa_cfg_offset)
 {
 	if (hw_type >= IPA_HW_v4_0) {
 		ctrl->ipa_clk_rate_turbo = IPA_V4_0_CLK_RATE_TURBO;
@@ -7466,7 +7466,8 @@ int ipa3_controller_static_bind(struct ipa3_controller *ctrl,
 		IPA_V3_0_BW_THRESHOLD_NOMINAL_MBPS;
 	ctrl->clock_scaling_bw_threshold_turbo =
 		IPA_V3_0_BW_THRESHOLD_TURBO_MBPS;
-	ctrl->ipa_reg_base_ofst = ipahal_get_reg_base();
+	ctrl->ipa_reg_base_ofst = ipa_cfg_offset == 0 ?
+						ipahal_get_reg_base() : ipa_cfg_offset;
 	ctrl->ipa_init_sram = _ipa_init_sram_v3;
 	ctrl->ipa_sram_read_settings = _ipa_sram_settings_read_v3_0;
 	ctrl->ipa_init_hdr = _ipa_init_hdr_v3_0;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c

@@ -1861,7 +1861,7 @@ int ipahal_get_proc_ctx_needed_len(enum ipa_hdr_proc_type type)
 }
 
 int ipahal_init(enum ipa_hw_type ipa_hw_type, void __iomem *base,
-	struct device *ipa_pdev)
+	u32 ipa_cfg_offset, struct device *ipa_pdev)
 {
 	int result;
 
@@ -1901,6 +1901,7 @@ int ipahal_init(enum ipa_hw_type ipa_hw_type, void __iomem *base,
 
 	ipahal_ctx->hw_type = ipa_hw_type;
 	ipahal_ctx->base = base;
+	ipahal_ctx->ipa_cfg_offset = ipa_cfg_offset;
 	ipahal_ctx->ipa_pdev = ipa_pdev;
 
 	if (ipahal_reg_init(ipa_hw_type)) {

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h

@@ -694,7 +694,7 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
 int ipahal_get_proc_ctx_needed_len(enum ipa_hdr_proc_type type);
 
 int ipahal_init(enum ipa_hw_type ipa_hw_type, void __iomem *base,
-	struct device *ipa_pdev);
+    u32 ipa_cfg_offset, struct device *ipa_pdev);
 void ipahal_destroy(void);
 void ipahal_free_dma_mem(struct ipa_mem_buffer *mem);
 

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h

@@ -79,6 +79,7 @@
 struct ipahal_context {
 	enum ipa_hw_type hw_type;
 	void __iomem *base;
+    u32 ipa_cfg_offset;
 	struct dentry *dent;
 	struct device *ipa_pdev;
 	struct ipa_mem_buffer empty_fltrt_tbl;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

@@ -4757,7 +4757,10 @@ u32 ipahal_get_reg_nk_offset(enum ipahal_reg_name reg, u32 n, u32 k)
 
 u32 ipahal_get_reg_base(void)
 {
-	return 0x00040000;
+	if (ipahal_ctx->ipa_cfg_offset == 0)
+		return 0x00040000;
+	else
+		return ipahal_ctx->ipa_cfg_offset;
 }