display: add uapi and shared headers to techpack folder
Move vendor specific display headers from include/uapi and include/linux path to techpack/display. Change-Id: I766f15694020eff9e2f1a20504f828be78d4175f Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
此提交包含在：
Shashank Babu Chinta Venkata
2
include/Kbuild
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2
include/Kbuild
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# Top-level Makefile calls into asm-$(ARCH)
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# List only non-arch directories below
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5
include/linux/Kbuild
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5
include/linux/Kbuild
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# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
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header-y += sde_io_util.h
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header-y += sde_rsc.h
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107
include/linux/sde_io_util.h
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107
include/linux/sde_io_util.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __SDE_IO_UTIL_H__
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#define __SDE_IO_UTIL_H__
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/i2c.h>
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#include <linux/types.h>
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#ifdef DEBUG
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#define DEV_DBG(fmt, args...) pr_err(fmt, ##args)
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#else
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#define DEV_DBG(fmt, args...) pr_debug(fmt, ##args)
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#endif
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#define DEV_INFO(fmt, args...) pr_info(fmt, ##args)
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#define DEV_WARN(fmt, args...) pr_warn(fmt, ##args)
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#define DEV_ERR(fmt, args...) pr_err(fmt, ##args)
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struct dss_io_data {
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u32 len;
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void __iomem *base;
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};
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void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug);
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u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug);
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void dss_reg_dump(void __iomem *base, u32 len, const char *prefix, u32 debug);
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#define DSS_REG_W_ND(io, offset, val) dss_reg_w(io, offset, val, false)
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#define DSS_REG_W(io, offset, val) dss_reg_w(io, offset, val, true)
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#define DSS_REG_R_ND(io, offset) dss_reg_r(io, offset, false)
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#define DSS_REG_R(io, offset) dss_reg_r(io, offset, true)
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enum dss_vreg_type {
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DSS_REG_LDO,
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DSS_REG_VS,
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};
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struct dss_vreg {
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struct regulator *vreg; /* vreg handle */
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char vreg_name[32];
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int min_voltage;
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int max_voltage;
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int enable_load;
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int disable_load;
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int pre_on_sleep;
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int post_on_sleep;
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int pre_off_sleep;
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int post_off_sleep;
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};
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struct dss_gpio {
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unsigned int gpio;
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unsigned int value;
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char gpio_name[32];
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};
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enum dss_clk_type {
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DSS_CLK_AHB, /* no set rate. rate controlled through rpm */
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DSS_CLK_PCLK,
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DSS_CLK_OTHER,
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};
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struct dss_clk {
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struct clk *clk; /* clk handle */
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char clk_name[32];
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enum dss_clk_type type;
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unsigned long rate;
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unsigned long max_rate;
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};
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struct dss_module_power {
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unsigned int num_vreg;
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struct dss_vreg *vreg_config;
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unsigned int num_gpio;
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struct dss_gpio *gpio_config;
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unsigned int num_clk;
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struct dss_clk *clk_config;
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};
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int msm_dss_ioremap_byname(struct platform_device *pdev,
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struct dss_io_data *io_data, const char *name);
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void msm_dss_iounmap(struct dss_io_data *io_data);
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int msm_dss_enable_gpio(struct dss_gpio *in_gpio, int num_gpio, int enable);
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int msm_dss_gpio_enable(struct dss_gpio *in_gpio, int num_gpio, int enable);
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int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg,
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int num_vreg, int config);
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int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable);
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int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
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void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
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int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
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int msm_dss_single_clk_set_rate(struct dss_clk *clk);
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int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
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int sde_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
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uint8_t reg_offset, uint8_t *read_buf);
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int sde_i2c_byte_write(struct i2c_client *client, uint8_t slave_addr,
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uint8_t reg_offset, uint8_t *value);
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#endif /* __SDE_IO_UTIL_H__ */
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359
include/linux/sde_rsc.h
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359
include/linux/sde_rsc.h
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@@ -0,0 +1,359 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_RSC_H_
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#define _SDE_RSC_H_
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#include <linux/kernel.h>
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/* primary display rsc index */
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#define SDE_RSC_INDEX 0
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#define MAX_RSC_CLIENT_NAME_LEN 128
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/* DRM Object IDs are numbered excluding 0, use 0 to indicate invalid CRTC */
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#define SDE_RSC_INVALID_CRTC_ID 0
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/**
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* event will be triggered before sde core power collapse,
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* mdss gdsc is still on
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*/
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#define SDE_RSC_EVENT_PRE_CORE_PC 0x1
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/**
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* event will be triggered after sde core collapse complete,
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* mdss gdsc is off now
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*/
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#define SDE_RSC_EVENT_POST_CORE_PC 0x2
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/**
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* event will be triggered before restoring the sde core from power collapse,
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* mdss gdsc is still off
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*/
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#define SDE_RSC_EVENT_PRE_CORE_RESTORE 0x4
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/**
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* event will be triggered after restoring the sde core from power collapse,
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* mdss gdsc is on now
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*/
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#define SDE_RSC_EVENT_POST_CORE_RESTORE 0x8
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/**
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* event attached with solver state enabled
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* all clients in clk_state or cmd_state
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*/
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#define SDE_RSC_EVENT_SOLVER_ENABLED 0x10
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/**
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* event attached with solver state disabled
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* one of the client requested for vid state
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*/
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#define SDE_RSC_EVENT_SOLVER_DISABLED 0x20
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/**
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* sde_rsc_client_type: sde rsc client type information
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* SDE_RSC_PRIMARY_DISP_CLIENT: A primary display client which can request
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* vid or cmd state switch.
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* SDE_RSC_EXTERNAL_DISPLAY_CLIENT:An external display client which can
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* request only clk state switch.
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* SDE_RSC_CLK_CLIENT: A clk client request for only rsc clocks
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* enabled and mode_2 exit state.
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*/
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enum sde_rsc_client_type {
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SDE_RSC_PRIMARY_DISP_CLIENT,
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SDE_RSC_EXTERNAL_DISP_CLIENT,
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SDE_RSC_CLK_CLIENT,
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SDE_RSC_INVALID_CLIENT,
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};
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/**
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* sde_rsc_state: sde rsc state information
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* SDE_RSC_IDLE_STATE: A client requests for idle state when there is no
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* pixel or cmd transfer expected. An idle vote from
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* all clients lead to power collapse state.
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* SDE_RSC_CLK_STATE: A client requests for clk state when it wants to
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* only avoid mode-2 entry/exit. For ex: V4L2 driver,
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* sde power handle, etc.
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* SDE_RSC_CMD_STATE: A client requests for cmd state when it wants to
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* enable the solver mode.
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* SDE_RSC_VID_STATE: A client requests for vid state it wants to avoid
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* solver enable because client is fetching data from
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* continuously.
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*/
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enum sde_rsc_state {
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SDE_RSC_IDLE_STATE,
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SDE_RSC_CLK_STATE,
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SDE_RSC_CMD_STATE,
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SDE_RSC_VID_STATE,
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};
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/**
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* struct sde_rsc_client: stores the rsc client for sde driver
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* @name: name of the client
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* @current_state: current client state
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* @crtc_id: crtc_id associated with this rsc client.
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* @rsc_index: rsc index of a client - only index "0" valid.
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* @id: Index of client. It will be assigned during client_create call
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* @client_type: check sde_rsc_client_type information
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* @list: list to attach client master list
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*/
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struct sde_rsc_client {
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char name[MAX_RSC_CLIENT_NAME_LEN];
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short current_state;
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int crtc_id;
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u32 rsc_index;
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u32 id;
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enum sde_rsc_client_type client_type;
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struct list_head list;
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};
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/**
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* struct sde_rsc_event: local event registration entry structure
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* @cb_func: Pointer to desired callback function
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* @usr: User pointer to pass to callback on event trigger
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* @rsc_index: rsc index of a client - only index "0" valid.
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* @event_type: refer comments in event_register
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* @list: list to attach event master list
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*/
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struct sde_rsc_event {
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void (*cb_func)(uint32_t event_type, void *usr);
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void *usr;
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u32 rsc_index;
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uint32_t event_type;
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struct list_head list;
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};
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/**
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* struct sde_rsc_cmd_config: provides panel configuration to rsc
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* when client is command mode. It is not required to set it during
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* video mode.
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*
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* @fps: panel te interval
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* @vtotal: current vertical total (height + vbp + vfp)
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* @jitter_numer: panel jitter numerator value. This config causes rsc/solver
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* early before te. Default is 0.8% jitter.
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* @jitter_denom: panel jitter denominator.
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* @prefill_lines: max prefill lines based on panel
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*/
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struct sde_rsc_cmd_config {
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u32 fps;
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u32 vtotal;
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u32 jitter_numer;
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u32 jitter_denom;
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u32 prefill_lines;
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};
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#ifdef CONFIG_DRM_SDE_RSC
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/**
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* sde_rsc_client_create() - create the client for sde rsc.
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* Different displays like DSI, HDMI, DP, WB, etc should call this
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* api to register their vote for rpmh. They still need to vote for
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* power handle to get the clocks.
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* @rsc_index: A client will be created on this RSC. As of now only
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* SDE_RSC_INDEX is valid rsc index.
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* @name: Caller needs to provide some valid string to identify
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* the client. "primary", "dp", "hdmi" are suggested name.
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* @client_type: check client_type enum for information
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* @vsync_source: This parameter is only valid for primary display. It provides
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* vsync source information
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*
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* Return: client node pointer.
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*/
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struct sde_rsc_client *sde_rsc_client_create(u32 rsc_index, char *name,
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enum sde_rsc_client_type client_type, u32 vsync_source);
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/**
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* sde_rsc_client_destroy() - Destroy the sde rsc client.
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*
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* @client: Client pointer provided by sde_rsc_client_create().
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*
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* Return: none
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*/
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void sde_rsc_client_destroy(struct sde_rsc_client *client);
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/**
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* sde_rsc_client_state_update() - rsc client state update
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* Video mode, cmd mode and clk state are supported as modes. A client need to
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* set this property during panel time. A switching client can set the
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* property to change the state
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*
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* @client: Client pointer provided by sde_rsc_client_create().
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* @state: Client state - video/cmd
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* @config: fps, vtotal, porches, etc configuration for command mode
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* panel
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* @crtc_id: current client's crtc id
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* @wait_vblank_crtc_id: Output parameter. If set to non-zero, rsc hw
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* state update requires a wait for one vblank on
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* the primary crtc. In that case, this output
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* param will be set to the crtc on which to wait.
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* If SDE_RSC_INVALID_CRTC_ID, no wait necessary
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*
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* Return: error code.
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*/
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int sde_rsc_client_state_update(struct sde_rsc_client *client,
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enum sde_rsc_state state,
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struct sde_rsc_cmd_config *config, int crtc_id,
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int *wait_vblank_crtc_id);
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/**
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* sde_rsc_client_get_vsync_refcount() - returns the status of the vsync
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* refcount, to signal if the client needs to reset the refcounting logic
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* @client: Client pointer provided by sde_rsc_client_create().
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*
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* Return: true if the state update has completed.
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*/
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int sde_rsc_client_get_vsync_refcount(
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struct sde_rsc_client *caller_client);
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/**
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* sde_rsc_client_reset_vsync_refcount() - reduces the refcounting
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* logic that waits for the vsync.
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* @client: Client pointer provided by sde_rsc_client_create().
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*
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* Return: true if the state update has completed.
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*/
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int sde_rsc_client_reset_vsync_refcount(
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struct sde_rsc_client *caller_client);
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/**
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* sde_rsc_client_is_state_update_complete() - check if state update is complete
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* RSC state transition is not complete until HW receives VBLANK signal. This
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* function checks RSC HW to determine whether that signal has been received.
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* @client: Client pointer provided by sde_rsc_client_create().
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*
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* Return: true if the state update has completed.
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*/
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bool sde_rsc_client_is_state_update_complete(
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struct sde_rsc_client *caller_client);
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/**
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* sde_rsc_client_vote() - stores ab/ib vote for rsc client
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*
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* @client: Client pointer provided by sde_rsc_client_create().
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* @bus_id: data bus identifier
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* @ab: aggregated bandwidth vote from client.
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* @ib: instant bandwidth vote from client.
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*
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* Return: error code.
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*/
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int sde_rsc_client_vote(struct sde_rsc_client *caller_client,
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u32 bus_id, u64 ab_vote, u64 ib_vote);
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/**
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* sde_rsc_register_event - register a callback function for an event
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* @rsc_index: A client will be created on this RSC. As of now only
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* SDE_RSC_INDEX is valid rsc index.
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* @event_type: event type to register; client sets 0x3 if it wants
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* to register for CORE_PC and CORE_RESTORE - both events.
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* @cb_func: Pointer to desired callback function
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* @usr: User pointer to pass to callback on event trigger
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* Returns: sde_rsc_event pointer on success
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*/
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struct sde_rsc_event *sde_rsc_register_event(int rsc_index, uint32_t event_type,
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void (*cb_func)(uint32_t event_type, void *usr), void *usr);
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/**
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* sde_rsc_unregister_event - unregister callback for an event
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* @sde_rsc_event: event returned by sde_rsc_register_event
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*/
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void sde_rsc_unregister_event(struct sde_rsc_event *event);
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/**
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* is_sde_rsc_available - check if display rsc available.
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* @rsc_index: A client will be created on this RSC. As of now only
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* SDE_RSC_INDEX is valid rsc index.
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* Returns: true if rsc is available; false in all other cases
|
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*/
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bool is_sde_rsc_available(int rsc_index);
|
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/**
|
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* get_sde_rsc_current_state - gets the current state of sde rsc.
|
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* @rsc_index: A client will be created on this RSC. As of now only
|
||||
* SDE_RSC_INDEX is valid rsc index.
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* Returns: current state if rsc available; SDE_RSC_IDLE_STATE for
|
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* all other cases
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*/
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enum sde_rsc_state get_sde_rsc_current_state(int rsc_index);
|
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/**
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* sde_rsc_client_trigger_vote() - triggers ab/ib vote for rsc client
|
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*
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* @client: Client pointer provided by sde_rsc_client_create().
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* @delta_vote: if bw vote is increased or decreased
|
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*
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* Return: error code.
|
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*/
|
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int sde_rsc_client_trigger_vote(struct sde_rsc_client *caller_client,
|
||||
bool delta_vote);
|
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|
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#else
|
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|
||||
static inline struct sde_rsc_client *sde_rsc_client_create(u32 rsc_index,
|
||||
char *name, enum sde_rsc_client_type client_type, u32 vsync_source)
|
||||
{
|
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return NULL;
|
||||
}
|
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|
||||
static inline void sde_rsc_client_destroy(struct sde_rsc_client *client)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int sde_rsc_client_state_update(struct sde_rsc_client *client,
|
||||
enum sde_rsc_state state,
|
||||
struct sde_rsc_cmd_config *config, int crtc_id,
|
||||
int *wait_vblank_crtc_id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int sde_rsc_client_get_vsync_refcount(
|
||||
struct sde_rsc_client *caller_client)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int sde_rsc_client_reset_vsync_refcount(
|
||||
struct sde_rsc_client *caller_client)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool sde_rsc_client_is_state_update_complete(
|
||||
struct sde_rsc_client *caller_client)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int sde_rsc_client_vote(struct sde_rsc_client *caller_client,
|
||||
u32 bus_id, u64 ab_vote, u64 ib_vote)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline struct sde_rsc_event *sde_rsc_register_event(int rsc_index,
|
||||
uint32_t event_type,
|
||||
void (*cb_func)(uint32_t event_type, void *usr), void *usr)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void sde_rsc_unregister_event(struct sde_rsc_event *event)
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool is_sde_rsc_available(int rsc_index)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline enum sde_rsc_state get_sde_rsc_current_state(int rsc_index)
|
||||
{
|
||||
return SDE_RSC_IDLE_STATE;
|
||||
}
|
||||
|
||||
static inline int sde_rsc_client_trigger_vote(
|
||||
struct sde_rsc_client *caller_client, bool delta_vote)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DRM_SDE_RSC */
|
||||
|
||||
#endif /* _SDE_RSC_H_ */
|
||||
4
include/uapi/Kbuild
一般檔案
4
include/uapi/Kbuild
一般檔案
@@ -0,0 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
|
||||
|
||||
header-y += media/
|
||||
header-y += drm/
|
||||
5
include/uapi/drm/Kbuild
一般檔案
5
include/uapi/drm/Kbuild
一般檔案
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
|
||||
|
||||
header-y += msm_drm_pp.h
|
||||
header-y += sde_drm.h
|
||||
|
||||
573
include/uapi/drm/msm_drm_pp.h
一般檔案
573
include/uapi/drm/msm_drm_pp.h
一般檔案
@@ -0,0 +1,573 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
|
||||
/*
|
||||
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _MSM_DRM_PP_H_
|
||||
#define _MSM_DRM_PP_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
/**
|
||||
* struct drm_msm_pcc_coeff - PCC coefficient structure for each color
|
||||
* component.
|
||||
* @c: constant coefficient.
|
||||
* @r: red coefficient.
|
||||
* @g: green coefficient.
|
||||
* @b: blue coefficient.
|
||||
* @rg: red green coefficient.
|
||||
* @gb: green blue coefficient.
|
||||
* @rb: red blue coefficient.
|
||||
* @rgb: red blue green coefficient.
|
||||
*/
|
||||
|
||||
struct drm_msm_pcc_coeff {
|
||||
__u32 c;
|
||||
__u32 r;
|
||||
__u32 g;
|
||||
__u32 b;
|
||||
__u32 rg;
|
||||
__u32 gb;
|
||||
__u32 rb;
|
||||
__u32 rgb;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_pcc - pcc feature structure
|
||||
* @flags: for customizing operations
|
||||
* @r: red coefficients.
|
||||
* @g: green coefficients.
|
||||
* @b: blue coefficients.
|
||||
* @r_rr: second order coefficients
|
||||
* @r_gg: second order coefficients
|
||||
* @r_bb: second order coefficients
|
||||
* @g_rr: second order coefficients
|
||||
* @g_gg: second order coefficients
|
||||
* @g_bb: second order coefficients
|
||||
* @b_rr: second order coefficients
|
||||
* @b_gg: second order coefficients
|
||||
* @b_bb: second order coefficients
|
||||
*/
|
||||
#define DRM_MSM_PCC3
|
||||
struct drm_msm_pcc {
|
||||
__u64 flags;
|
||||
struct drm_msm_pcc_coeff r;
|
||||
struct drm_msm_pcc_coeff g;
|
||||
struct drm_msm_pcc_coeff b;
|
||||
__u32 r_rr;
|
||||
__u32 r_gg;
|
||||
__u32 r_bb;
|
||||
__u32 g_rr;
|
||||
__u32 g_gg;
|
||||
__u32 g_bb;
|
||||
__u32 b_rr;
|
||||
__u32 b_gg;
|
||||
__u32 b_bb;
|
||||
};
|
||||
|
||||
/* struct drm_msm_pa_vlut - picture adjustment vLUT structure
|
||||
* flags: for customizing vlut operation
|
||||
* val: vLUT values
|
||||
*/
|
||||
#define PA_VLUT_SIZE 256
|
||||
struct drm_msm_pa_vlut {
|
||||
__u64 flags;
|
||||
__u32 val[PA_VLUT_SIZE];
|
||||
};
|
||||
|
||||
#define PA_HSIC_HUE_ENABLE (1 << 0)
|
||||
#define PA_HSIC_SAT_ENABLE (1 << 1)
|
||||
#define PA_HSIC_VAL_ENABLE (1 << 2)
|
||||
#define PA_HSIC_CONT_ENABLE (1 << 3)
|
||||
/**
|
||||
* struct drm_msm_pa_hsic - pa hsic feature structure
|
||||
* @flags: flags for the feature customization, values can be:
|
||||
* - PA_HSIC_HUE_ENABLE: Enable hue adjustment
|
||||
* - PA_HSIC_SAT_ENABLE: Enable saturation adjustment
|
||||
* - PA_HSIC_VAL_ENABLE: Enable value adjustment
|
||||
* - PA_HSIC_CONT_ENABLE: Enable contrast adjustment
|
||||
*
|
||||
* @hue: hue setting
|
||||
* @saturation: saturation setting
|
||||
* @value: value setting
|
||||
* @contrast: contrast setting
|
||||
*/
|
||||
#define DRM_MSM_PA_HSIC
|
||||
struct drm_msm_pa_hsic {
|
||||
__u64 flags;
|
||||
__u32 hue;
|
||||
__u32 saturation;
|
||||
__u32 value;
|
||||
__u32 contrast;
|
||||
};
|
||||
|
||||
#define MEMCOL_PROT_HUE (1 << 0)
|
||||
#define MEMCOL_PROT_SAT (1 << 1)
|
||||
#define MEMCOL_PROT_VAL (1 << 2)
|
||||
#define MEMCOL_PROT_CONT (1 << 3)
|
||||
#define MEMCOL_PROT_SIXZONE (1 << 4)
|
||||
#define MEMCOL_PROT_BLEND (1 << 5)
|
||||
/* struct drm_msm_memcol - Memory color feature structure.
|
||||
* Skin, sky, foliage features are supported.
|
||||
* @prot_flags: Bit mask for enabling protection feature.
|
||||
* @color_adjust_p0: Adjustment curve.
|
||||
* @color_adjust_p1: Adjustment curve.
|
||||
* @color_adjust_p2: Adjustment curve.
|
||||
* @blend_gain: Blend gain weightage from othe PA features.
|
||||
* @sat_hold: Saturation hold value.
|
||||
* @val_hold: Value hold info.
|
||||
* @hue_region: Hue qualifier.
|
||||
* @sat_region: Saturation qualifier.
|
||||
* @val_region: Value qualifier.
|
||||
*/
|
||||
#define DRM_MSM_MEMCOL
|
||||
struct drm_msm_memcol {
|
||||
__u64 prot_flags;
|
||||
__u32 color_adjust_p0;
|
||||
__u32 color_adjust_p1;
|
||||
__u32 color_adjust_p2;
|
||||
__u32 blend_gain;
|
||||
__u32 sat_hold;
|
||||
__u32 val_hold;
|
||||
__u32 hue_region;
|
||||
__u32 sat_region;
|
||||
__u32 val_region;
|
||||
};
|
||||
|
||||
#define DRM_MSM_SIXZONE
|
||||
#define SIXZONE_LUT_SIZE 384
|
||||
#define SIXZONE_HUE_ENABLE (1 << 0)
|
||||
#define SIXZONE_SAT_ENABLE (1 << 1)
|
||||
#define SIXZONE_VAL_ENABLE (1 << 2)
|
||||
/* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure.
|
||||
* @p0: Hue adjustment.
|
||||
* @p1: Saturation/Value adjustment.
|
||||
*/
|
||||
struct drm_msm_sixzone_curve {
|
||||
__u32 p1;
|
||||
__u32 p0;
|
||||
};
|
||||
|
||||
/* struct drm_msm_sixzone - Sixzone feature structure.
|
||||
* @flags: for feature customization, values can be:
|
||||
* - SIXZONE_HUE_ENABLE: Enable hue adjustment
|
||||
* - SIXZONE_SAT_ENABLE: Enable saturation adjustment
|
||||
* - SIXZONE_VAL_ENABLE: Enable value adjustment
|
||||
* @threshold: threshold qualifier.
|
||||
* @adjust_p0: Adjustment curve.
|
||||
* @adjust_p1: Adjustment curve.
|
||||
* @sat_hold: Saturation hold info.
|
||||
* @val_hold: Value hold info.
|
||||
* @curve: HSV adjustment curve lut.
|
||||
*/
|
||||
struct drm_msm_sixzone {
|
||||
__u64 flags;
|
||||
__u32 threshold;
|
||||
__u32 adjust_p0;
|
||||
__u32 adjust_p1;
|
||||
__u32 sat_hold;
|
||||
__u32 val_hold;
|
||||
struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
|
||||
};
|
||||
|
||||
#define GAMUT_3D_MODE_17 1
|
||||
#define GAMUT_3D_MODE_5 2
|
||||
#define GAMUT_3D_MODE_13 3
|
||||
|
||||
#define GAMUT_3D_MODE17_TBL_SZ 1229
|
||||
#define GAMUT_3D_MODE5_TBL_SZ 32
|
||||
#define GAMUT_3D_MODE13_TBL_SZ 550
|
||||
#define GAMUT_3D_SCALE_OFF_SZ 16
|
||||
#define GAMUT_3D_SCALEB_OFF_SZ 12
|
||||
#define GAMUT_3D_TBL_NUM 4
|
||||
#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
|
||||
#define GAMUT_3D_MAP_EN (1 << 0)
|
||||
|
||||
/**
|
||||
* struct drm_msm_3d_col - 3d gamut color component structure
|
||||
* @c0: Holds c0 value
|
||||
* @c2_c1: Holds c2/c1 values
|
||||
*/
|
||||
struct drm_msm_3d_col {
|
||||
__u32 c2_c1;
|
||||
__u32 c0;
|
||||
};
|
||||
/**
|
||||
* struct drm_msm_3d_gamut - 3d gamut feature structure
|
||||
* @flags: flags for the feature values are:
|
||||
* 0 - no map
|
||||
* GAMUT_3D_MAP_EN - enable map
|
||||
* @mode: lut mode can take following values:
|
||||
* - GAMUT_3D_MODE_17
|
||||
* - GAMUT_3D_MODE_5
|
||||
* - GAMUT_3D_MODE_13
|
||||
* @scale_off: Scale offset table
|
||||
* @col: Color component tables
|
||||
*/
|
||||
struct drm_msm_3d_gamut {
|
||||
__u64 flags;
|
||||
__u32 mode;
|
||||
__u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
|
||||
struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
|
||||
};
|
||||
|
||||
#define PGC_TBL_LEN 512
|
||||
#define PGC_8B_ROUND (1 << 0)
|
||||
/**
|
||||
* struct drm_msm_pgc_lut - pgc lut feature structure
|
||||
* @flags: flags for the featue values can be:
|
||||
* - PGC_8B_ROUND
|
||||
* @c0: color0 component lut
|
||||
* @c1: color1 component lut
|
||||
* @c2: color2 component lut
|
||||
*/
|
||||
struct drm_msm_pgc_lut {
|
||||
__u64 flags;
|
||||
__u32 c0[PGC_TBL_LEN];
|
||||
__u32 c1[PGC_TBL_LEN];
|
||||
__u32 c2[PGC_TBL_LEN];
|
||||
};
|
||||
|
||||
#define IGC_TBL_LEN 256
|
||||
#define IGC_DITHER_ENABLE (1 << 0)
|
||||
/**
|
||||
* struct drm_msm_igc_lut - igc lut feature structure
|
||||
* @flags: flags for the feature customization, values can be:
|
||||
* - IGC_DITHER_ENABLE: Enable dither functionality
|
||||
* @c0: color0 component lut
|
||||
* @c1: color1 component lut
|
||||
* @c2: color2 component lut
|
||||
* @strength: dither strength, considered valid when IGC_DITHER_ENABLE
|
||||
* is set in flags. Strength value based on source bit width.
|
||||
* @c0_last: color0 lut_last component
|
||||
* @c1_last: color1 lut_last component
|
||||
* @c2_last: color2 lut_last component
|
||||
*/
|
||||
struct drm_msm_igc_lut {
|
||||
__u64 flags;
|
||||
__u32 c0[IGC_TBL_LEN];
|
||||
__u32 c1[IGC_TBL_LEN];
|
||||
__u32 c2[IGC_TBL_LEN];
|
||||
__u32 strength;
|
||||
__u32 c0_last;
|
||||
__u32 c1_last;
|
||||
__u32 c2_last;
|
||||
};
|
||||
#define LAST_LUT 2
|
||||
|
||||
#define HIST_V_SIZE 256
|
||||
/**
|
||||
* struct drm_msm_hist - histogram feature structure
|
||||
* @flags: for customizing operations
|
||||
* @data: histogram data
|
||||
*/
|
||||
struct drm_msm_hist {
|
||||
__u64 flags;
|
||||
__u32 data[HIST_V_SIZE];
|
||||
};
|
||||
|
||||
#define AD4_LUT_GRP0_SIZE 33
|
||||
#define AD4_LUT_GRP1_SIZE 32
|
||||
/*
|
||||
* struct drm_msm_ad4_init - ad4 init structure set by user-space client.
|
||||
* Init param values can change based on tuning
|
||||
* hence it is passed by user-space clients.
|
||||
*/
|
||||
struct drm_msm_ad4_init {
|
||||
__u32 init_param_001[AD4_LUT_GRP0_SIZE];
|
||||
__u32 init_param_002[AD4_LUT_GRP0_SIZE];
|
||||
__u32 init_param_003[AD4_LUT_GRP0_SIZE];
|
||||
__u32 init_param_004[AD4_LUT_GRP0_SIZE];
|
||||
__u32 init_param_005[AD4_LUT_GRP1_SIZE];
|
||||
__u32 init_param_006[AD4_LUT_GRP1_SIZE];
|
||||
__u32 init_param_007[AD4_LUT_GRP0_SIZE];
|
||||
__u32 init_param_008[AD4_LUT_GRP0_SIZE];
|
||||
__u32 init_param_009;
|
||||
__u32 init_param_010;
|
||||
__u32 init_param_011;
|
||||
__u32 init_param_012;
|
||||
__u32 init_param_013;
|
||||
__u32 init_param_014;
|
||||
__u32 init_param_015;
|
||||
__u32 init_param_016;
|
||||
__u32 init_param_017;
|
||||
__u32 init_param_018;
|
||||
__u32 init_param_019;
|
||||
__u32 init_param_020;
|
||||
__u32 init_param_021;
|
||||
__u32 init_param_022;
|
||||
__u32 init_param_023;
|
||||
__u32 init_param_024;
|
||||
__u32 init_param_025;
|
||||
__u32 init_param_026;
|
||||
__u32 init_param_027;
|
||||
__u32 init_param_028;
|
||||
__u32 init_param_029;
|
||||
__u32 init_param_030;
|
||||
__u32 init_param_031;
|
||||
__u32 init_param_032;
|
||||
__u32 init_param_033;
|
||||
__u32 init_param_034;
|
||||
__u32 init_param_035;
|
||||
__u32 init_param_036;
|
||||
__u32 init_param_037;
|
||||
__u32 init_param_038;
|
||||
__u32 init_param_039;
|
||||
__u32 init_param_040;
|
||||
__u32 init_param_041;
|
||||
__u32 init_param_042;
|
||||
__u32 init_param_043;
|
||||
__u32 init_param_044;
|
||||
__u32 init_param_045;
|
||||
__u32 init_param_046;
|
||||
__u32 init_param_047;
|
||||
__u32 init_param_048;
|
||||
__u32 init_param_049;
|
||||
__u32 init_param_050;
|
||||
__u32 init_param_051;
|
||||
__u32 init_param_052;
|
||||
__u32 init_param_053;
|
||||
__u32 init_param_054;
|
||||
__u32 init_param_055;
|
||||
__u32 init_param_056;
|
||||
__u32 init_param_057;
|
||||
__u32 init_param_058;
|
||||
__u32 init_param_059;
|
||||
__u32 init_param_060;
|
||||
__u32 init_param_061;
|
||||
__u32 init_param_062;
|
||||
__u32 init_param_063;
|
||||
__u32 init_param_064;
|
||||
__u32 init_param_065;
|
||||
__u32 init_param_066;
|
||||
__u32 init_param_067;
|
||||
__u32 init_param_068;
|
||||
__u32 init_param_069;
|
||||
__u32 init_param_070;
|
||||
__u32 init_param_071;
|
||||
__u32 init_param_072;
|
||||
__u32 init_param_073;
|
||||
__u32 init_param_074;
|
||||
__u32 init_param_075;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ad4_cfg - ad4 config structure set by user-space client.
|
||||
* Config param values can vary based on tuning,
|
||||
* hence it is passed by user-space clients.
|
||||
*/
|
||||
struct drm_msm_ad4_cfg {
|
||||
__u32 cfg_param_001;
|
||||
__u32 cfg_param_002;
|
||||
__u32 cfg_param_003;
|
||||
__u32 cfg_param_004;
|
||||
__u32 cfg_param_005;
|
||||
__u32 cfg_param_006;
|
||||
__u32 cfg_param_007;
|
||||
__u32 cfg_param_008;
|
||||
__u32 cfg_param_009;
|
||||
__u32 cfg_param_010;
|
||||
__u32 cfg_param_011;
|
||||
__u32 cfg_param_012;
|
||||
__u32 cfg_param_013;
|
||||
__u32 cfg_param_014;
|
||||
__u32 cfg_param_015;
|
||||
__u32 cfg_param_016;
|
||||
__u32 cfg_param_017;
|
||||
__u32 cfg_param_018;
|
||||
__u32 cfg_param_019;
|
||||
__u32 cfg_param_020;
|
||||
__u32 cfg_param_021;
|
||||
__u32 cfg_param_022;
|
||||
__u32 cfg_param_023;
|
||||
__u32 cfg_param_024;
|
||||
__u32 cfg_param_025;
|
||||
__u32 cfg_param_026;
|
||||
__u32 cfg_param_027;
|
||||
__u32 cfg_param_028;
|
||||
__u32 cfg_param_029;
|
||||
__u32 cfg_param_030;
|
||||
__u32 cfg_param_031;
|
||||
__u32 cfg_param_032;
|
||||
__u32 cfg_param_033;
|
||||
__u32 cfg_param_034;
|
||||
__u32 cfg_param_035;
|
||||
__u32 cfg_param_036;
|
||||
__u32 cfg_param_037;
|
||||
__u32 cfg_param_038;
|
||||
__u32 cfg_param_039;
|
||||
__u32 cfg_param_040;
|
||||
__u32 cfg_param_041;
|
||||
__u32 cfg_param_042;
|
||||
__u32 cfg_param_043;
|
||||
__u32 cfg_param_044;
|
||||
__u32 cfg_param_045;
|
||||
__u32 cfg_param_046;
|
||||
__u32 cfg_param_047;
|
||||
__u32 cfg_param_048;
|
||||
__u32 cfg_param_049;
|
||||
__u32 cfg_param_050;
|
||||
__u32 cfg_param_051;
|
||||
__u32 cfg_param_052;
|
||||
__u32 cfg_param_053;
|
||||
};
|
||||
|
||||
#define DITHER_MATRIX_SZ 16
|
||||
|
||||
/**
|
||||
* struct drm_msm_dither - dither feature structure
|
||||
* @flags: for customizing operations
|
||||
* @temporal_en: temperal dither enable
|
||||
* @c0_bitdepth: c0 component bit depth
|
||||
* @c1_bitdepth: c1 component bit depth
|
||||
* @c2_bitdepth: c2 component bit depth
|
||||
* @c3_bitdepth: c2 component bit depth
|
||||
* @matrix: dither strength matrix
|
||||
*/
|
||||
struct drm_msm_dither {
|
||||
__u64 flags;
|
||||
__u32 temporal_en;
|
||||
__u32 c0_bitdepth;
|
||||
__u32 c1_bitdepth;
|
||||
__u32 c2_bitdepth;
|
||||
__u32 c3_bitdepth;
|
||||
__u32 matrix[DITHER_MATRIX_SZ];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_pa_dither - dspp dither feature structure
|
||||
* @flags: for customizing operations
|
||||
* @strength: dither strength
|
||||
* @offset_en: offset enable bit
|
||||
* @matrix: dither data matrix
|
||||
*/
|
||||
#define DRM_MSM_PA_DITHER
|
||||
struct drm_msm_pa_dither {
|
||||
__u64 flags;
|
||||
__u32 strength;
|
||||
__u32 offset_en;
|
||||
__u32 matrix[DITHER_MATRIX_SZ];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_ad4_roi_cfg - ad4 roi params config set
|
||||
* by user-space client.
|
||||
* @h_x - hotizontal direction start
|
||||
* @h_y - hotizontal direction end
|
||||
* @v_x - vertical direction start
|
||||
* @v_y - vertical direction end
|
||||
* @factor_in - the alpha value for inside roi region
|
||||
* @factor_out - the alpha value for outside roi region
|
||||
*/
|
||||
#define DRM_MSM_AD4_ROI
|
||||
struct drm_msm_ad4_roi_cfg {
|
||||
__u32 h_x;
|
||||
__u32 h_y;
|
||||
__u32 v_x;
|
||||
__u32 v_y;
|
||||
__u32 factor_in;
|
||||
__u32 factor_out;
|
||||
};
|
||||
|
||||
#define LTM_FEATURE_DEF 1
|
||||
#define LTM_DATA_SIZE_0 32
|
||||
#define LTM_DATA_SIZE_1 128
|
||||
#define LTM_DATA_SIZE_2 256
|
||||
#define LTM_DATA_SIZE_3 33
|
||||
#define LTM_BUFFER_SIZE 5
|
||||
#define LTM_GUARD_BYTES 255
|
||||
#define LTM_BLOCK_SIZE 2
|
||||
|
||||
#define LTM_STATS_SAT (1 << 1)
|
||||
#define LTM_STATS_MERGE_SAT (1 << 2)
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_stats_data - LTM stats data structure
|
||||
*/
|
||||
struct drm_msm_ltm_stats_data {
|
||||
__u32 stats_01[LTM_DATA_SIZE_0][LTM_DATA_SIZE_1];
|
||||
__u32 stats_02[LTM_DATA_SIZE_2];
|
||||
__u32 stats_03[LTM_DATA_SIZE_0];
|
||||
__u32 stats_04[LTM_DATA_SIZE_0];
|
||||
__u32 stats_05[LTM_DATA_SIZE_0];
|
||||
__u32 status_flag;
|
||||
__u32 display_h;
|
||||
__u32 display_v;
|
||||
__u32 init_h[LTM_BLOCK_SIZE];
|
||||
__u32 init_v;
|
||||
__u32 inc_h;
|
||||
__u32 inc_v;
|
||||
__u32 portrait_en;
|
||||
__u32 merge_en;
|
||||
__u32 cfg_param_01;
|
||||
__u32 cfg_param_02;
|
||||
__u32 cfg_param_03;
|
||||
__u32 cfg_param_04;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_init_param - LTM init param structure
|
||||
*/
|
||||
struct drm_msm_ltm_init_param {
|
||||
__u32 init_param_01;
|
||||
__u32 init_param_02;
|
||||
__u32 init_param_03;
|
||||
__u32 init_param_04;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_cfg_param - LTM config param structure
|
||||
*/
|
||||
struct drm_msm_ltm_cfg_param {
|
||||
__u32 cfg_param_01;
|
||||
__u32 cfg_param_02;
|
||||
__u32 cfg_param_03;
|
||||
__u32 cfg_param_04;
|
||||
__u32 cfg_param_05;
|
||||
__u32 cfg_param_06;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_data - LTM data structure
|
||||
*/
|
||||
struct drm_msm_ltm_data {
|
||||
__u32 data[LTM_DATA_SIZE_0][LTM_DATA_SIZE_3];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_buffers_crtl - LTM buffer control structure.
|
||||
* This struct will be used to init and
|
||||
* de-init the LTM buffers in driver.
|
||||
* @num_of_buffers: valid number of buffers used
|
||||
* @fds: fd array to for all the valid buffers
|
||||
*/
|
||||
struct drm_msm_ltm_buffers_ctrl {
|
||||
__u32 num_of_buffers;
|
||||
__u32 fds[LTM_BUFFER_SIZE];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_buffer - LTM buffer structure.
|
||||
* This struct will be passed from driver to user
|
||||
* space for LTM stats data notification.
|
||||
* @fd: fd assicated with the buffer that has LTM stats data
|
||||
* @offset: offset from base address that used for alignment
|
||||
* @status status flag for error indication
|
||||
*/
|
||||
struct drm_msm_ltm_buffer {
|
||||
__u32 fd;
|
||||
__u32 offset;
|
||||
__u32 status;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_ad4_manual_str_cfg - ad4 manual strength config set
|
||||
* by user-space client.
|
||||
* @in_str - strength for inside roi region
|
||||
* @out_str - strength for outside roi region
|
||||
*/
|
||||
#define DRM_MSM_AD4_MANUAL_STRENGTH
|
||||
struct drm_msm_ad4_manual_str_cfg {
|
||||
__u32 in_str;
|
||||
__u32 out_str;
|
||||
};
|
||||
#endif /* _MSM_DRM_PP_H_ */
|
||||
649
include/uapi/drm/sde_drm.h
一般檔案
649
include/uapi/drm/sde_drm.h
一般檔案
@@ -0,0 +1,649 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
|
||||
/*
|
||||
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _SDE_DRM_H_
|
||||
#define _SDE_DRM_H_
|
||||
|
||||
#include <drm/drm.h>
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Total number of supported color planes */
|
||||
#define SDE_MAX_PLANES 4
|
||||
|
||||
/* Total number of parameterized detail enhancer mapping curves */
|
||||
#define SDE_MAX_DE_CURVES 3
|
||||
|
||||
/* Y/RGB and UV filter configuration */
|
||||
#define FILTER_EDGE_DIRECTED_2D 0x0
|
||||
#define FILTER_CIRCULAR_2D 0x1
|
||||
#define FILTER_SEPARABLE_1D 0x2
|
||||
#define FILTER_BILINEAR 0x3
|
||||
|
||||
/* Alpha filters */
|
||||
#define FILTER_ALPHA_DROP_REPEAT 0x0
|
||||
#define FILTER_ALPHA_BILINEAR 0x1
|
||||
#define FILTER_ALPHA_2D 0x3
|
||||
|
||||
/* Blend filters */
|
||||
#define FILTER_BLEND_CIRCULAR_2D 0x0
|
||||
#define FILTER_BLEND_SEPARABLE_1D 0x1
|
||||
|
||||
/* LUT configuration flags */
|
||||
#define SCALER_LUT_SWAP 0x1
|
||||
#define SCALER_LUT_DIR_WR 0x2
|
||||
#define SCALER_LUT_Y_CIR_WR 0x4
|
||||
#define SCALER_LUT_UV_CIR_WR 0x8
|
||||
#define SCALER_LUT_Y_SEP_WR 0x10
|
||||
#define SCALER_LUT_UV_SEP_WR 0x20
|
||||
|
||||
/**
|
||||
* Blend operations for "blend_op" property
|
||||
*
|
||||
* @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
|
||||
* @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
|
||||
* would appear opaque in case fg plane alpha
|
||||
* is 0xff.
|
||||
* @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
|
||||
* has alpha pre-multiplication done. If the fg
|
||||
* plane alpha is less than 0xff, apply
|
||||
* modulation as well. This operation is
|
||||
* intended on layers having alpha channel.
|
||||
* @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not
|
||||
* alpha pre-multiplied. Apply
|
||||
* pre-multiplication. If fg plane alpha is
|
||||
* less than 0xff, apply modulation as well.
|
||||
* @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation
|
||||
* possible by mdp.
|
||||
*/
|
||||
#define SDE_DRM_BLEND_OP_NOT_DEFINED 0
|
||||
#define SDE_DRM_BLEND_OP_OPAQUE 1
|
||||
#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2
|
||||
#define SDE_DRM_BLEND_OP_COVERAGE 3
|
||||
#define SDE_DRM_BLEND_OP_MAX 4
|
||||
|
||||
/**
|
||||
* Bit masks for "src_config" property
|
||||
* construct bitmask via (1UL << SDE_DRM_<flag>)
|
||||
*/
|
||||
#define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */
|
||||
|
||||
/* DRM bitmasks are restricted to 0..63 */
|
||||
#define SDE_DRM_BITMASK_COUNT 64
|
||||
|
||||
/**
|
||||
* Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property
|
||||
*
|
||||
* @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode
|
||||
* is non-secure domain and requires
|
||||
* both stage I and stage II translations when
|
||||
* this buffer is accessed by the display HW.
|
||||
* This is the default mode of all frambuffers.
|
||||
* @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode
|
||||
* is secure domain and requires
|
||||
* both stage I and stage II translations when
|
||||
* this buffer is accessed by the display HW.
|
||||
* @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
|
||||
* is non-secure domain and requires
|
||||
* only stage II translation when
|
||||
* this buffer is accessed by the display HW.
|
||||
* @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
|
||||
* is secure domain and requires
|
||||
* only stage II translation when
|
||||
* this buffer is accessed by the display HW.
|
||||
*/
|
||||
|
||||
#define SDE_DRM_FB_NON_SEC 0
|
||||
#define SDE_DRM_FB_SEC 1
|
||||
#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2
|
||||
#define SDE_DRM_FB_SEC_DIR_TRANS 3
|
||||
|
||||
/**
|
||||
* Secure levels for "security_level" CRTC property.
|
||||
* CRTC property which specifies what plane types
|
||||
* can be attached to this CRTC. Plane component
|
||||
* derives the plane type based on the FB_MODE.
|
||||
* @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be
|
||||
* attached to this CRTC. This is the default state of
|
||||
* the CRTC.
|
||||
* @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a
|
||||
* CRTC is instructed to be in this mode it follows the
|
||||
* platform dependent restrictions.
|
||||
*/
|
||||
#define SDE_DRM_SEC_NON_SEC 0
|
||||
#define SDE_DRM_SEC_ONLY 1
|
||||
|
||||
/**
|
||||
* struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure
|
||||
* @num_ext_pxls_lr: Number of total horizontal pixels
|
||||
* @num_ext_pxls_tb: Number of total vertical lines
|
||||
* @left_ftch: Number of extra pixels to overfetch from left
|
||||
* @right_ftch: Number of extra pixels to overfetch from right
|
||||
* @top_ftch: Number of extra lines to overfetch from top
|
||||
* @btm_ftch: Number of extra lines to overfetch from bottom
|
||||
* @left_rpt: Number of extra pixels to repeat from left
|
||||
* @right_rpt: Number of extra pixels to repeat from right
|
||||
* @top_rpt: Number of extra lines to repeat from top
|
||||
* @btm_rpt: Number of extra lines to repeat from bottom
|
||||
*/
|
||||
struct sde_drm_pix_ext_v1 {
|
||||
/*
|
||||
* Number of pixels ext in left, right, top and bottom direction
|
||||
* for all color components.
|
||||
*/
|
||||
int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
|
||||
int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
|
||||
|
||||
/*
|
||||
* Number of pixels needs to be overfetched in left, right, top
|
||||
* and bottom directions from source image for scaling.
|
||||
*/
|
||||
int32_t left_ftch[SDE_MAX_PLANES];
|
||||
int32_t right_ftch[SDE_MAX_PLANES];
|
||||
int32_t top_ftch[SDE_MAX_PLANES];
|
||||
int32_t btm_ftch[SDE_MAX_PLANES];
|
||||
/*
|
||||
* Number of pixels needs to be repeated in left, right, top and
|
||||
* bottom directions for scaling.
|
||||
*/
|
||||
int32_t left_rpt[SDE_MAX_PLANES];
|
||||
int32_t right_rpt[SDE_MAX_PLANES];
|
||||
int32_t top_rpt[SDE_MAX_PLANES];
|
||||
int32_t btm_rpt[SDE_MAX_PLANES];
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler
|
||||
* @lr: Pixel extension settings for left/right
|
||||
* @tb: Pixel extension settings for top/botton
|
||||
* @init_phase_x: Initial scaler phase values for x
|
||||
* @phase_step_x: Phase step values for x
|
||||
* @init_phase_y: Initial scaler phase values for y
|
||||
* @phase_step_y: Phase step values for y
|
||||
* @horz_filter: Horizontal filter array
|
||||
* @vert_filter: Vertical filter array
|
||||
*/
|
||||
struct sde_drm_scaler_v1 {
|
||||
/*
|
||||
* Pix ext settings
|
||||
*/
|
||||
struct sde_drm_pix_ext_v1 pe;
|
||||
/*
|
||||
* Phase settings
|
||||
*/
|
||||
int32_t init_phase_x[SDE_MAX_PLANES];
|
||||
int32_t phase_step_x[SDE_MAX_PLANES];
|
||||
int32_t init_phase_y[SDE_MAX_PLANES];
|
||||
int32_t phase_step_y[SDE_MAX_PLANES];
|
||||
|
||||
/*
|
||||
* Filter type to be used for scaling in horizontal and vertical
|
||||
* directions
|
||||
*/
|
||||
uint32_t horz_filter[SDE_MAX_PLANES];
|
||||
uint32_t vert_filter[SDE_MAX_PLANES];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sde_drm_de_v1 - version 1 of detail enhancer structure
|
||||
* @enable: Enables/disables detail enhancer
|
||||
* @sharpen_level1: Sharpening strength for noise
|
||||
* @sharpen_level2: Sharpening strength for context
|
||||
* @clip: Clip coefficient
|
||||
* @limit: Detail enhancer limit factor
|
||||
* @thr_quiet: Quite zone threshold
|
||||
* @thr_dieout: Die-out zone threshold
|
||||
* @thr_low: Linear zone left threshold
|
||||
* @thr_high: Linear zone right threshold
|
||||
* @prec_shift: Detail enhancer precision
|
||||
* @adjust_a: Mapping curves A coefficients
|
||||
* @adjust_b: Mapping curves B coefficients
|
||||
* @adjust_c: Mapping curves C coefficients
|
||||
*/
|
||||
struct sde_drm_de_v1 {
|
||||
uint32_t enable;
|
||||
int16_t sharpen_level1;
|
||||
int16_t sharpen_level2;
|
||||
uint16_t clip;
|
||||
uint16_t limit;
|
||||
uint16_t thr_quiet;
|
||||
uint16_t thr_dieout;
|
||||
uint16_t thr_low;
|
||||
uint16_t thr_high;
|
||||
uint16_t prec_shift;
|
||||
int16_t adjust_a[SDE_MAX_DE_CURVES];
|
||||
int16_t adjust_b[SDE_MAX_DE_CURVES];
|
||||
int16_t adjust_c[SDE_MAX_DE_CURVES];
|
||||
};
|
||||
|
||||
/*
|
||||
* Scaler configuration flags
|
||||
*/
|
||||
|
||||
/* Disable dynamic expansion */
|
||||
#define SDE_DYN_EXP_DISABLE 0x1
|
||||
|
||||
#define SDE_DRM_QSEED3LITE
|
||||
#define SDE_DRM_QSEED4
|
||||
|
||||
/**
|
||||
* struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
|
||||
* @enable: Scaler enable
|
||||
* @dir_en: Detail enhancer enable
|
||||
* @pe: Pixel extension settings
|
||||
* @horz_decimate: Horizontal decimation factor
|
||||
* @vert_decimate: Vertical decimation factor
|
||||
* @init_phase_x: Initial scaler phase values for x
|
||||
* @phase_step_x: Phase step values for x
|
||||
* @init_phase_y: Initial scaler phase values for y
|
||||
* @phase_step_y: Phase step values for y
|
||||
* @preload_x: Horizontal preload value
|
||||
* @preload_y: Vertical preload value
|
||||
* @src_width: Source width
|
||||
* @src_height: Source height
|
||||
* @dst_width: Destination width
|
||||
* @dst_height: Destination height
|
||||
* @y_rgb_filter_cfg: Y/RGB plane filter configuration
|
||||
* @uv_filter_cfg: UV plane filter configuration
|
||||
* @alpha_filter_cfg: Alpha filter configuration
|
||||
* @blend_cfg: Selection of blend coefficients
|
||||
* @lut_flag: LUT configuration flags
|
||||
* @dir_lut_idx: 2d 4x4 LUT index
|
||||
* @y_rgb_cir_lut_idx: Y/RGB circular LUT index
|
||||
* @uv_cir_lut_idx: UV circular LUT index
|
||||
* @y_rgb_sep_lut_idx: Y/RGB separable LUT index
|
||||
* @uv_sep_lut_idx: UV separable LUT index
|
||||
* @de: Detail enhancer settings
|
||||
* @dir_weight: Directional Weight
|
||||
* @unsharp_mask_blend: Unsharp Blend Filter Ratio
|
||||
* @de_blend: Ratio of two unsharp mask filters
|
||||
* @flags: Scaler configuration flags
|
||||
*/
|
||||
struct sde_drm_scaler_v2 {
|
||||
/*
|
||||
* General definitions
|
||||
*/
|
||||
uint32_t enable;
|
||||
uint32_t dir_en;
|
||||
|
||||
/*
|
||||
* Pix ext settings
|
||||
*/
|
||||
struct sde_drm_pix_ext_v1 pe;
|
||||
|
||||
/*
|
||||
* Decimation settings
|
||||
*/
|
||||
uint32_t horz_decimate;
|
||||
uint32_t vert_decimate;
|
||||
|
||||
/*
|
||||
* Phase settings
|
||||
*/
|
||||
int32_t init_phase_x[SDE_MAX_PLANES];
|
||||
int32_t phase_step_x[SDE_MAX_PLANES];
|
||||
int32_t init_phase_y[SDE_MAX_PLANES];
|
||||
int32_t phase_step_y[SDE_MAX_PLANES];
|
||||
|
||||
uint32_t preload_x[SDE_MAX_PLANES];
|
||||
uint32_t preload_y[SDE_MAX_PLANES];
|
||||
uint32_t src_width[SDE_MAX_PLANES];
|
||||
uint32_t src_height[SDE_MAX_PLANES];
|
||||
|
||||
uint32_t dst_width;
|
||||
uint32_t dst_height;
|
||||
|
||||
uint32_t y_rgb_filter_cfg;
|
||||
uint32_t uv_filter_cfg;
|
||||
uint32_t alpha_filter_cfg;
|
||||
uint32_t blend_cfg;
|
||||
|
||||
uint32_t lut_flag;
|
||||
uint32_t dir_lut_idx;
|
||||
|
||||
/* for Y(RGB) and UV planes*/
|
||||
uint32_t y_rgb_cir_lut_idx;
|
||||
uint32_t uv_cir_lut_idx;
|
||||
uint32_t y_rgb_sep_lut_idx;
|
||||
uint32_t uv_sep_lut_idx;
|
||||
|
||||
/*
|
||||
* Detail enhancer settings
|
||||
*/
|
||||
struct sde_drm_de_v1 de;
|
||||
uint32_t dir_weight;
|
||||
uint32_t unsharp_mask_blend;
|
||||
uint32_t de_blend;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
/* Number of dest scalers supported */
|
||||
#define SDE_MAX_DS_COUNT 2
|
||||
|
||||
/*
|
||||
* Destination scaler flag config
|
||||
*/
|
||||
#define SDE_DRM_DESTSCALER_ENABLE 0x1
|
||||
#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2
|
||||
#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4
|
||||
#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8
|
||||
|
||||
/**
|
||||
* struct sde_drm_dest_scaler_cfg - destination scaler config structure
|
||||
* @flags: Flag to switch between mode for destination scaler
|
||||
* refer to destination scaler flag config
|
||||
* @index: Destination scaler selection index
|
||||
* @lm_width: Layer mixer width configuration
|
||||
* @lm_height: Layer mixer height configuration
|
||||
* @scaler_cfg: The scaling parameters for all the mode except disable
|
||||
* Userspace pointer to struct sde_drm_scaler_v2
|
||||
*/
|
||||
struct sde_drm_dest_scaler_cfg {
|
||||
uint32_t flags;
|
||||
uint32_t index;
|
||||
uint32_t lm_width;
|
||||
uint32_t lm_height;
|
||||
uint64_t scaler_cfg;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sde_drm_dest_scaler_data - destination scaler data struct
|
||||
* @num_dest_scaler: Number of dest scalers to be configured
|
||||
* @ds_cfg: Destination scaler block configuration
|
||||
*/
|
||||
struct sde_drm_dest_scaler_data {
|
||||
uint32_t num_dest_scaler;
|
||||
struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT];
|
||||
};
|
||||
|
||||
/*
|
||||
* Define constants for struct sde_drm_csc
|
||||
*/
|
||||
#define SDE_CSC_MATRIX_COEFF_SIZE 9
|
||||
#define SDE_CSC_CLAMP_SIZE 6
|
||||
#define SDE_CSC_BIAS_SIZE 3
|
||||
|
||||
/**
|
||||
* struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc
|
||||
* @ctm_coeff: Matrix coefficients, in S31.32 format
|
||||
* @pre_bias: Pre-bias array values
|
||||
* @post_bias: Post-bias array values
|
||||
* @pre_clamp: Pre-clamp array values
|
||||
* @post_clamp: Post-clamp array values
|
||||
*/
|
||||
struct sde_drm_csc_v1 {
|
||||
int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
|
||||
uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
|
||||
uint32_t post_bias[SDE_CSC_BIAS_SIZE];
|
||||
uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
|
||||
uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sde_drm_color - struct to store the color and alpha values
|
||||
* @color_0: Color 0 value
|
||||
* @color_1: Color 1 value
|
||||
* @color_2: Color 2 value
|
||||
* @color_3: Color 3 value
|
||||
*/
|
||||
struct sde_drm_color {
|
||||
uint32_t color_0;
|
||||
uint32_t color_1;
|
||||
uint32_t color_2;
|
||||
uint32_t color_3;
|
||||
};
|
||||
|
||||
/* Total number of supported dim layers */
|
||||
#define SDE_MAX_DIM_LAYERS 7
|
||||
|
||||
/* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */
|
||||
/* Color fill inside of the rect, including border */
|
||||
#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1
|
||||
/* Color fill outside of the rect, excluding border */
|
||||
#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2
|
||||
|
||||
/**
|
||||
* struct sde_drm_dim_layer - dim layer cfg struct
|
||||
* @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values
|
||||
* @stage: Blending stage of the dim layer
|
||||
* @color_fill: Color fill for dim layer
|
||||
* @rect: Dim layer coordinates
|
||||
*/
|
||||
struct sde_drm_dim_layer_cfg {
|
||||
uint32_t flags;
|
||||
uint32_t stage;
|
||||
struct sde_drm_color color_fill;
|
||||
struct drm_clip_rect rect;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sde_drm_dim_layer_v1 - version 1 of dim layer struct
|
||||
* @num_layers: Numer of Dim Layers
|
||||
* @layer: Dim layer user cfgs ptr for the num_layers
|
||||
*/
|
||||
struct sde_drm_dim_layer_v1 {
|
||||
uint32_t num_layers;
|
||||
struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS];
|
||||
};
|
||||
|
||||
/* Writeback Config version definition */
|
||||
#define SDE_DRM_WB_CFG 0x1
|
||||
|
||||
/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */
|
||||
#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0)
|
||||
|
||||
/**
|
||||
* struct sde_drm_wb_cfg - Writeback configuration structure
|
||||
* @flags: see DRM_MSM_WB_CONFIG_FLAGS
|
||||
* @connector_id: writeback connector identifier
|
||||
* @count_modes: Count of modes in modes_ptr
|
||||
* @modes: Pointer to struct drm_mode_modeinfo
|
||||
*/
|
||||
struct sde_drm_wb_cfg {
|
||||
uint32_t flags;
|
||||
uint32_t connector_id;
|
||||
uint32_t count_modes;
|
||||
uint64_t modes;
|
||||
};
|
||||
|
||||
#define SDE_MAX_ROI_V1 4
|
||||
|
||||
/**
|
||||
* struct sde_drm_roi_v1 - list of regions of interest for a drm object
|
||||
* @num_rects: number of valid rectangles in the roi array
|
||||
* @roi: list of roi rectangles
|
||||
*/
|
||||
struct sde_drm_roi_v1 {
|
||||
uint32_t num_rects;
|
||||
struct drm_clip_rect roi[SDE_MAX_ROI_V1];
|
||||
};
|
||||
|
||||
/**
|
||||
* Define extended power modes supported by the SDE connectors.
|
||||
*/
|
||||
#define SDE_MODE_DPMS_ON 0
|
||||
#define SDE_MODE_DPMS_LP1 1
|
||||
#define SDE_MODE_DPMS_LP2 2
|
||||
#define SDE_MODE_DPMS_STANDBY 3
|
||||
#define SDE_MODE_DPMS_SUSPEND 4
|
||||
#define SDE_MODE_DPMS_OFF 5
|
||||
|
||||
/**
|
||||
* sde recovery events for notifying client
|
||||
*/
|
||||
#define SDE_RECOVERY_SUCCESS 0
|
||||
#define SDE_RECOVERY_CAPTURE 1
|
||||
#define SDE_RECOVERY_HARD_RESET 2
|
||||
|
||||
/*
|
||||
* Colorimetry Data Block values
|
||||
* These bit nums are defined as per the CTA spec
|
||||
* and indicate the colorspaces supported by the sink
|
||||
*/
|
||||
#define DRM_EDID_CLRMETRY_xvYCC_601 (1 << 0)
|
||||
#define DRM_EDID_CLRMETRY_xvYCC_709 (1 << 1)
|
||||
#define DRM_EDID_CLRMETRY_sYCC_601 (1 << 2)
|
||||
#define DRM_EDID_CLRMETRY_ADOBE_YCC_601 (1 << 3)
|
||||
#define DRM_EDID_CLRMETRY_ADOBE_RGB (1 << 4)
|
||||
#define DRM_EDID_CLRMETRY_BT2020_CYCC (1 << 5)
|
||||
#define DRM_EDID_CLRMETRY_BT2020_YCC (1 << 6)
|
||||
#define DRM_EDID_CLRMETRY_BT2020_RGB (1 << 7)
|
||||
#define DRM_EDID_CLRMETRY_DCI_P3 (1 << 15)
|
||||
|
||||
/*
|
||||
* HDR Metadata
|
||||
* These are defined as per EDID spec and shall be used by the sink
|
||||
* to set the HDR metadata for playback from userspace.
|
||||
*/
|
||||
|
||||
#define HDR_PRIMARIES_COUNT 3
|
||||
|
||||
/* HDR EOTF */
|
||||
#define HDR_EOTF_SDR_LUM_RANGE 0x0
|
||||
#define HDR_EOTF_HDR_LUM_RANGE 0x1
|
||||
#define HDR_EOTF_SMTPE_ST2084 0x2
|
||||
#define HDR_EOTF_HLG 0x3
|
||||
|
||||
#define DRM_MSM_EXT_HDR_METADATA
|
||||
#define DRM_MSM_EXT_HDR_PLUS_METADATA
|
||||
struct drm_msm_ext_hdr_metadata {
|
||||
__u32 hdr_state; /* HDR state */
|
||||
__u32 eotf; /* electro optical transfer function */
|
||||
__u32 hdr_supported; /* HDR supported */
|
||||
__u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */
|
||||
__u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */
|
||||
__u32 white_point_x; /* white_point_x */
|
||||
__u32 white_point_y; /* white_point_y */
|
||||
__u32 max_luminance; /* Max luminance */
|
||||
__u32 min_luminance; /* Min Luminance */
|
||||
__u32 max_content_light_level; /* max content light level */
|
||||
__u32 max_average_light_level; /* max average light level */
|
||||
|
||||
__u64 hdr_plus_payload; /* user pointer to dynamic HDR payload */
|
||||
__u32 hdr_plus_payload_size;/* size of dynamic HDR payload data */
|
||||
};
|
||||
|
||||
/**
|
||||
* HDR sink properties
|
||||
* These are defined as per EDID spec and shall be used by the userspace
|
||||
* to determine the HDR properties to be set to the sink.
|
||||
*/
|
||||
#define DRM_MSM_EXT_HDR_PROPERTIES
|
||||
#define DRM_MSM_EXT_HDR_PLUS_PROPERTIES
|
||||
struct drm_msm_ext_hdr_properties {
|
||||
__u8 hdr_metadata_type_one; /* static metadata type one */
|
||||
__u32 hdr_supported; /* HDR supported */
|
||||
__u32 hdr_eotf; /* electro optical transfer function */
|
||||
__u32 hdr_max_luminance; /* Max luminance */
|
||||
__u32 hdr_avg_luminance; /* Avg luminance */
|
||||
__u32 hdr_min_luminance; /* Min Luminance */
|
||||
|
||||
__u32 hdr_plus_supported; /* HDR10+ supported */
|
||||
};
|
||||
|
||||
/* HDR WRGB x and y index */
|
||||
#define DISPLAY_PRIMARIES_WX 0
|
||||
#define DISPLAY_PRIMARIES_WY 1
|
||||
#define DISPLAY_PRIMARIES_RX 2
|
||||
#define DISPLAY_PRIMARIES_RY 3
|
||||
#define DISPLAY_PRIMARIES_GX 4
|
||||
#define DISPLAY_PRIMARIES_GY 5
|
||||
#define DISPLAY_PRIMARIES_BX 6
|
||||
#define DISPLAY_PRIMARIES_BY 7
|
||||
#define DISPLAY_PRIMARIES_MAX 8
|
||||
|
||||
struct drm_panel_hdr_properties {
|
||||
__u32 hdr_enabled;
|
||||
|
||||
/* WRGB X and y values arrayed in format */
|
||||
/* [WX, WY, RX, RY, GX, GY, BX, BY] */
|
||||
__u32 display_primaries[DISPLAY_PRIMARIES_MAX];
|
||||
|
||||
/* peak brightness supported by panel */
|
||||
__u32 peak_brightness;
|
||||
/* Blackness level supported by panel */
|
||||
__u32 blackness_level;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_event_req - Payload to event enable/disable ioctls.
|
||||
* @object_id: DRM object id. e.g.: for crtc pass crtc id.
|
||||
* @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC.
|
||||
* @event: Event for which notification is being enabled/disabled.
|
||||
* e.g.: for Histogram set - DRM_EVENT_HISTOGRAM.
|
||||
* @client_context: Opaque pointer that will be returned during event response
|
||||
* notification.
|
||||
* @index: Object index(e.g.: crtc index), optional for user-space to set.
|
||||
* Driver will override value based on object_id and object_type.
|
||||
*/
|
||||
struct drm_msm_event_req {
|
||||
__u32 object_id;
|
||||
__u32 object_type;
|
||||
__u32 event;
|
||||
__u64 client_context;
|
||||
__u32 index;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_event_resp - payload returned when read is called for
|
||||
* custom notifications.
|
||||
* @base: Event type and length of complete notification payload.
|
||||
* @info: Contains information about DRM that which raised this event.
|
||||
* @data: Custom payload that driver returns for event type.
|
||||
* size of data = base.length - (sizeof(base) + sizeof(info))
|
||||
*/
|
||||
struct drm_msm_event_resp {
|
||||
struct drm_event base;
|
||||
struct drm_msm_event_req info;
|
||||
__u8 data[];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_power_ctrl: Payload to enable/disable the power vote
|
||||
* @enable: enable/disable the power vote
|
||||
* @flags: operation control flags, for future use
|
||||
*/
|
||||
struct drm_msm_power_ctrl {
|
||||
__u32 enable;
|
||||
__u32 flags;
|
||||
};
|
||||
#define DRM_SDE_WB_CONFIG 0x40
|
||||
#define DRM_MSM_REGISTER_EVENT 0x41
|
||||
#define DRM_MSM_DEREGISTER_EVENT 0x42
|
||||
#define DRM_MSM_RMFB2 0x43
|
||||
#define DRM_MSM_POWER_CTRL 0x44
|
||||
|
||||
/* sde custom events */
|
||||
#define DRM_EVENT_HISTOGRAM 0x80000000
|
||||
#define DRM_EVENT_AD_BACKLIGHT 0x80000001
|
||||
#define DRM_EVENT_CRTC_POWER 0x80000002
|
||||
#define DRM_EVENT_SYS_BACKLIGHT 0x80000003
|
||||
#define DRM_EVENT_SDE_POWER 0x80000004
|
||||
#define DRM_EVENT_IDLE_NOTIFY 0x80000005
|
||||
#define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */
|
||||
#define DRM_EVENT_SDE_HW_RECOVERY 0X80000007
|
||||
#define DRM_EVENT_LTM_HIST 0X80000008
|
||||
#define DRM_EVENT_LTM_WB_PB 0X80000009
|
||||
#define DRM_EVENT_LTM_OFF 0X8000000A
|
||||
|
||||
#define DRM_IOCTL_SDE_WB_CONFIG \
|
||||
DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
|
||||
#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
|
||||
DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req)
|
||||
#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
|
||||
DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req)
|
||||
#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \
|
||||
DRM_MSM_RMFB2), unsigned int)
|
||||
#define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + \
|
||||
DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SDE_DRM_H_ */
|
||||
3
include/uapi/media/Kbuild
一般檔案
3
include/uapi/media/Kbuild
一般檔案
@@ -0,0 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
|
||||
|
||||
header-y += msm_sde_rotator.h
|
||||
122
include/uapi/media/msm_sde_rotator.h
一般檔案
122
include/uapi/media/msm_sde_rotator.h
一般檔案
@@ -0,0 +1,122 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
|
||||
/*
|
||||
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __UAPI_MSM_SDE_ROTATOR_H__
|
||||
#define __UAPI_MSM_SDE_ROTATOR_H__
|
||||
|
||||
#include <linux/videodev2.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
/* SDE Rotator pixel format definitions */
|
||||
#define SDE_PIX_FMT_XRGB_8888 V4L2_PIX_FMT_XBGR32
|
||||
#define SDE_PIX_FMT_ARGB_8888 V4L2_PIX_FMT_ABGR32
|
||||
#define SDE_PIX_FMT_ABGR_8888 V4L2_PIX_FMT_SDE_ABGR_8888
|
||||
#define SDE_PIX_FMT_RGBA_8888 V4L2_PIX_FMT_SDE_RGBA_8888
|
||||
#define SDE_PIX_FMT_BGRA_8888 V4L2_PIX_FMT_ARGB32
|
||||
#define SDE_PIX_FMT_RGBX_8888 V4L2_PIX_FMT_SDE_RGBX_8888
|
||||
#define SDE_PIX_FMT_BGRX_8888 V4L2_PIX_FMT_XRGB32
|
||||
#define SDE_PIX_FMT_XBGR_8888 V4L2_PIX_FMT_SDE_XBGR_8888
|
||||
#define SDE_PIX_FMT_RGBA_5551 V4L2_PIX_FMT_SDE_RGBA_5551
|
||||
#define SDE_PIX_FMT_ARGB_1555 V4L2_PIX_FMT_ARGB555
|
||||
#define SDE_PIX_FMT_ABGR_1555 V4L2_PIX_FMT_SDE_ABGR_1555
|
||||
#define SDE_PIX_FMT_BGRA_5551 V4L2_PIX_FMT_SDE_BGRA_5551
|
||||
#define SDE_PIX_FMT_BGRX_5551 V4L2_PIX_FMT_SDE_BGRX_5551
|
||||
#define SDE_PIX_FMT_RGBX_5551 V4L2_PIX_FMT_SDE_RGBX_5551
|
||||
#define SDE_PIX_FMT_XBGR_1555 V4L2_PIX_FMT_SDE_XBGR_1555
|
||||
#define SDE_PIX_FMT_XRGB_1555 V4L2_PIX_FMT_XRGB555
|
||||
#define SDE_PIX_FMT_ARGB_4444 V4L2_PIX_FMT_ARGB444
|
||||
#define SDE_PIX_FMT_RGBA_4444 V4L2_PIX_FMT_SDE_RGBA_4444
|
||||
#define SDE_PIX_FMT_BGRA_4444 V4L2_PIX_FMT_SDE_BGRA_4444
|
||||
#define SDE_PIX_FMT_ABGR_4444 V4L2_PIX_FMT_SDE_ABGR_4444
|
||||
#define SDE_PIX_FMT_RGBX_4444 V4L2_PIX_FMT_SDE_RGBX_4444
|
||||
#define SDE_PIX_FMT_XRGB_4444 V4L2_PIX_FMT_XRGB444
|
||||
#define SDE_PIX_FMT_BGRX_4444 V4L2_PIX_FMT_SDE_BGRX_4444
|
||||
#define SDE_PIX_FMT_XBGR_4444 V4L2_PIX_FMT_SDE_XBGR_4444
|
||||
#define SDE_PIX_FMT_RGB_888 V4L2_PIX_FMT_RGB24
|
||||
#define SDE_PIX_FMT_BGR_888 V4L2_PIX_FMT_BGR24
|
||||
#define SDE_PIX_FMT_RGB_565 V4L2_PIX_FMT_RGB565
|
||||
#define SDE_PIX_FMT_BGR_565 V4L2_PIX_FMT_SDE_BGR_565
|
||||
#define SDE_PIX_FMT_Y_CB_CR_H2V2 V4L2_PIX_FMT_YUV420
|
||||
#define SDE_PIX_FMT_Y_CR_CB_H2V2 V4L2_PIX_FMT_YVU420
|
||||
#define SDE_PIX_FMT_Y_CR_CB_GH2V2 V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2 V4L2_PIX_FMT_NV12
|
||||
#define SDE_PIX_FMT_Y_CRCB_H2V2 V4L2_PIX_FMT_NV21
|
||||
#define SDE_PIX_FMT_Y_CBCR_H1V2 V4L2_PIX_FMT_SDE_Y_CBCR_H1V2
|
||||
#define SDE_PIX_FMT_Y_CRCB_H1V2 V4L2_PIX_FMT_SDE_Y_CRCB_H1V2
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V1 V4L2_PIX_FMT_NV16
|
||||
#define SDE_PIX_FMT_Y_CRCB_H2V1 V4L2_PIX_FMT_NV61
|
||||
#define SDE_PIX_FMT_YCBYCR_H2V1 V4L2_PIX_FMT_YUYV
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS
|
||||
#define SDE_PIX_FMT_Y_CRCB_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS
|
||||
#define SDE_PIX_FMT_RGBA_8888_UBWC V4L2_PIX_FMT_RGBA8888_UBWC
|
||||
#define SDE_PIX_FMT_RGBX_8888_UBWC V4L2_PIX_FMT_SDE_RGBX_8888_UBWC
|
||||
#define SDE_PIX_FMT_RGB_565_UBWC V4L2_PIX_FMT_SDE_RGB_565_UBWC
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_UBWC V4L2_PIX_FMT_NV12_UBWC
|
||||
#define SDE_PIX_FMT_RGBA_1010102 V4L2_PIX_FMT_SDE_RGBA_1010102
|
||||
#define SDE_PIX_FMT_RGBX_1010102 V4L2_PIX_FMT_SDE_RGBX_1010102
|
||||
#define SDE_PIX_FMT_ARGB_2101010 V4L2_PIX_FMT_SDE_ARGB_2101010
|
||||
#define SDE_PIX_FMT_XRGB_2101010 V4L2_PIX_FMT_SDE_XRGB_2101010
|
||||
#define SDE_PIX_FMT_BGRA_1010102 V4L2_PIX_FMT_SDE_BGRA_1010102
|
||||
#define SDE_PIX_FMT_BGRX_1010102 V4L2_PIX_FMT_SDE_BGRX_1010102
|
||||
#define SDE_PIX_FMT_ABGR_2101010 V4L2_PIX_FMT_SDE_ABGR_2101010
|
||||
#define SDE_PIX_FMT_XBGR_2101010 V4L2_PIX_FMT_SDE_XBGR_2101010
|
||||
#define SDE_PIX_FMT_RGBA_1010102_UBWC V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC
|
||||
#define SDE_PIX_FMT_RGBX_1010102_UBWC V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_VENUS \
|
||||
V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC V4L2_PIX_FMT_NV12_TP10_UBWC
|
||||
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_UBWC V4L2_PIX_FMT_NV12_P010_UBWC
|
||||
|
||||
/*
|
||||
* struct msm_sde_rotator_fence - v4l2 buffer fence info
|
||||
* @index: id number of the buffer
|
||||
* @type: enum v4l2_buf_type; buffer type
|
||||
* @fd: file descriptor of the fence associated with this buffer
|
||||
*/
|
||||
struct msm_sde_rotator_fence {
|
||||
__u32 index;
|
||||
__u32 type;
|
||||
__s32 fd;
|
||||
__u32 reserved[5];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct msm_sde_rotator_comp_ratio - v4l2 buffer compression ratio
|
||||
* @index: id number of the buffer
|
||||
* @type: enum v4l2_buf_type; buffer type
|
||||
* @numer: numerator of the ratio
|
||||
* @denom: denominator of the ratio
|
||||
*/
|
||||
struct msm_sde_rotator_comp_ratio {
|
||||
__u32 index;
|
||||
__u32 type;
|
||||
__u32 numer;
|
||||
__u32 denom;
|
||||
__u32 reserved[4];
|
||||
};
|
||||
|
||||
/* SDE Rotator private ioctl ID */
|
||||
#define VIDIOC_G_SDE_ROTATOR_FENCE \
|
||||
_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence)
|
||||
#define VIDIOC_S_SDE_ROTATOR_FENCE \
|
||||
_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence)
|
||||
#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO \
|
||||
_IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio)
|
||||
#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO \
|
||||
_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio)
|
||||
|
||||
/* SDE Rotator private control ID's */
|
||||
#define V4L2_CID_SDE_ROTATOR_SECURE (V4L2_CID_USER_BASE + 0x1000)
|
||||
|
||||
/*
|
||||
* This control Id indicates this context is associated with the
|
||||
* secure camera.
|
||||
*/
|
||||
#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA (V4L2_CID_USER_BASE + 0x2000)
|
||||
|
||||
#endif /* __UAPI_MSM_SDE_ROTATOR_H__ */
|
||||
@@ -44,6 +44,7 @@
|
||||
#include <drm/drm_plane_helper.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#include <drm/msm_drm.h>
|
||||
#include <drm/sde_drm.h>
|
||||
#include <drm/drm_gem.h>
|
||||
|
||||
#include "sde_power_handle.h"
|
||||
|
||||
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