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Merge "asoc: codecs: Tanggu TX RX changes"

Linux Build Service Account vor 6 Jahren
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b7d3f59c2a

+ 2 - 2
Android.mk

@@ -30,8 +30,8 @@ include $(MY_LOCAL_PATH)/asoc/codecs/aqt1000/Android.mk
 endif
 
 ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE)),true)
-$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/bolero/Module.symvers)
-include $(MY_LOCAL_PATH)/asoc/codecs/bolero/Android.mk
+$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers)
+include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk
 endif
 
 ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)

+ 1 - 0
asoc/codecs/Kbuild

@@ -190,6 +190,7 @@ ifeq ($(KERNEL_BUILD), 1)
 	obj-y	+= sdm660_cdc/
 	obj-y	+= msm_sdw/
 	obj-y	+= wcd9360/
+	obj-y	+= wcd937x/
 endif
 # Module information used by KBuild framework
 obj-$(CONFIG_WCD9XXX_CODEC_CORE) += wcd_core_dlkm.o

+ 57 - 0
asoc/codecs/wcd937x/Android.mk

@@ -0,0 +1,57 @@
+# Android makefile for audio kernel modules
+
+# Assume no targets will be supported
+
+# Check if this driver needs be built for current target
+ifeq ($(call is-board-platform,$(MSMSTEPPE)),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_SM6150=m
+endif
+
+AUDIO_CHIPSET := audio
+# Build/Package only in case of supported target
+ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE)),true)
+
+LOCAL_PATH := $(call my-dir)
+
+# This makefile is only for DLKM
+ifneq ($(findstring vendor,$(LOCAL_PATH)),)
+
+ifneq ($(findstring opensource,$(LOCAL_PATH)),)
+	AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel
+endif # opensource
+
+DLKM_DIR := $(TOP)/device/qcom/common/dlkm
+
+# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
+###########################################################
+# This is set once per LOCAL_PATH, not per (kernel) module
+KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
+
+# We are actually building audio.ko here, as per the
+# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
+# This means we need to rename the module to <chipset>_audio.ko
+# after audio.ko is built.
+KBUILD_OPTIONS += MODNAME=wcd937x_dlkm
+KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
+KBUILD_OPTIONS += $(AUDIO_SELECT)
+
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_MODULE              := $(AUDIO_CHIPSET)_wcd937x.ko
+LOCAL_MODULE_KBUILD_NAME  := wcd937x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/AndroidKernelModule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_MODULE              := $(AUDIO_CHIPSET)_wcd937x_slave.ko
+LOCAL_MODULE_KBUILD_NAME  := wcd937x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/AndroidKernelModule.mk
+###########################################################
+
+endif # DLKM check
+endif # supported target check

+ 112 - 0
asoc/codecs/wcd937x/Kbuild

@@ -0,0 +1,112 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.9
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_SM6150), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ WCD937X ############
+
+# for WCD937X Codec
+ifdef CONFIG_SND_SOC_WCD937X
+	WCD937X_OBJS += wcd937x.o
+	WCD937X_OBJS += wcd937x-regmap.o
+	WCD937X_OBJS += wcd937x-tables.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD937X_SLAVE
+	WCD937X_SLAVE_OBJS += wcd937x_slave.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_WCD937X) += wcd937x_dlkm.o
+wcd937x_dlkm-y := $(WCD937X_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD937X_SLAVE) += wcd937x_slave_dlkm.o
+wcd937x_slave_dlkm-y := $(WCD937X_SLAVE_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

+ 58 - 0
asoc/codecs/wcd937x/internal.h

@@ -0,0 +1,58 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _WCD937X_INTERNAL_H
+#define _WCD937X_INTERNAL_H
+
+#include "../wcd-mbhc-v2.h"
+
+#define WCD937X_MAX_MICBIAS 3
+
+extern struct regmap_config wcd937x_regmap_config;
+
+struct wcd937x_priv {
+	struct device *dev;
+
+	int variant;
+	struct snd_soc_codec *codec;
+	struct device_node *rst_np;
+	struct regmap *regmap;
+
+	struct swr_device *rx_swr_dev;
+	struct swr_device *tx_swr_dev;
+
+	s32 micb_ref[WCD937X_MAX_MICBIAS];
+	s32 pullup_ref[WCD937X_MAX_MICBIAS];
+
+	struct fw_info *fw_data;
+	struct device_node *wcd_rst_np;
+
+	s32 dmic_0_1_clk_cnt;
+	s32 dmic_2_3_clk_cnt;
+	s32 dmic_4_5_clk_cnt;
+	/* mbhc module */
+	struct wcd_mbhc mbhc;
+	struct blocking_notifier_head notifier;
+	struct mutex micb_lock;
+
+	u32 hph_mode;
+
+	u32 rx_clk_cnt;
+};
+
+struct wcd937x_pdata {
+	struct device_node *rst_np;
+	struct device_node *rx_slave;
+	struct device_node *tx_slave;
+};
+
+#endif

+ 446 - 0
asoc/codecs/wcd937x/wcd937x-registers.h

@@ -0,0 +1,446 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _WCD937X_REGISTERS_H
+#define _WCD937X_REGISTERS_H
+
+#define WCD937X_BASE_ADDRESS 0x3000
+
+#define WCD937X_REG(reg)  (reg - WCD937X_BASE_ADDRESS)
+
+enum {
+	REG_NO_ACCESS,
+	RD_REG,
+	WR_REG,
+	RD_WR_REG
+};
+
+#define WCD937X_ANA_BIAS                            (WCD937X_BASE_ADDRESS+0x001)
+#define WCD937X_ANA_RX_SUPPLIES                     (WCD937X_BASE_ADDRESS+0x008)
+#define WCD937X_ANA_HPH                             (WCD937X_BASE_ADDRESS+0x009)
+#define WCD937X_ANA_EAR                             (WCD937X_BASE_ADDRESS+0x00A)
+#define WCD937X_ANA_EAR_COMPANDER_CTL               (WCD937X_BASE_ADDRESS+0x00B)
+#define WCD937X_ANA_TX_CH1                          (WCD937X_BASE_ADDRESS+0x00E)
+#define WCD937X_ANA_TX_CH2                          (WCD937X_BASE_ADDRESS+0x00F)
+#define WCD937X_ANA_TX_CH3                          (WCD937X_BASE_ADDRESS+0x010)
+#define WCD937X_ANA_TX_CH3_HPF                      (WCD937X_BASE_ADDRESS+0x011)
+#define WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC        (WCD937X_BASE_ADDRESS+0x012)
+#define WCD937X_ANA_MICB3_DSP_EN_LOGIC              (WCD937X_BASE_ADDRESS+0x013)
+#define WCD937X_ANA_MBHC_MECH                       (WCD937X_BASE_ADDRESS+0x014)
+#define WCD937X_ANA_MBHC_ELECT                      (WCD937X_BASE_ADDRESS+0x015)
+#define WCD937X_ANA_MBHC_ZDET                       (WCD937X_BASE_ADDRESS+0x016)
+#define WCD937X_ANA_MBHC_RESULT_1                   (WCD937X_BASE_ADDRESS+0x017)
+#define WCD937X_ANA_MBHC_RESULT_2                   (WCD937X_BASE_ADDRESS+0x018)
+#define WCD937X_ANA_MBHC_RESULT_3                   (WCD937X_BASE_ADDRESS+0x019)
+#define WCD937X_ANA_MBHC_BTN0                       (WCD937X_BASE_ADDRESS+0x01A)
+#define WCD937X_ANA_MBHC_BTN1                       (WCD937X_BASE_ADDRESS+0x01B)
+#define WCD937X_ANA_MBHC_BTN2                       (WCD937X_BASE_ADDRESS+0x01C)
+#define WCD937X_ANA_MBHC_BTN3                       (WCD937X_BASE_ADDRESS+0x01D)
+#define WCD937X_ANA_MBHC_BTN4                       (WCD937X_BASE_ADDRESS+0x01E)
+#define WCD937X_ANA_MBHC_BTN5                       (WCD937X_BASE_ADDRESS+0x01F)
+#define WCD937X_ANA_MBHC_BTN6                       (WCD937X_BASE_ADDRESS+0x020)
+#define WCD937X_ANA_MBHC_BTN7                       (WCD937X_BASE_ADDRESS+0x021)
+#define WCD937X_ANA_MICB1                           (WCD937X_BASE_ADDRESS+0x022)
+#define WCD937X_ANA_MICB2                           (WCD937X_BASE_ADDRESS+0x023)
+#define WCD937X_ANA_MICB2_RAMP                      (WCD937X_BASE_ADDRESS+0x024)
+#define WCD937X_ANA_MICB3                           (WCD937X_BASE_ADDRESS+0x025)
+#define WCD937X_BIAS_CTL                            (WCD937X_BASE_ADDRESS+0x028)
+#define WCD937X_BIAS_VBG_FINE_ADJ                   (WCD937X_BASE_ADDRESS+0x029)
+#define WCD937X_LDOL_VDDCX_ADJUST                   (WCD937X_BASE_ADDRESS+0x040)
+#define WCD937X_LDOL_DISABLE_LDOL                   (WCD937X_BASE_ADDRESS+0x041)
+#define WCD937X_MBHC_CTL_CLK                        (WCD937X_BASE_ADDRESS+0x056)
+#define WCD937X_MBHC_CTL_ANA                        (WCD937X_BASE_ADDRESS+0x057)
+#define WCD937X_MBHC_CTL_SPARE_1                    (WCD937X_BASE_ADDRESS+0x058)
+#define WCD937X_MBHC_CTL_SPARE_2                    (WCD937X_BASE_ADDRESS+0x059)
+#define WCD937X_MBHC_CTL_BCS                        (WCD937X_BASE_ADDRESS+0x05A)
+#define WCD937X_MBHC_MOISTURE_DET_FSM_STATUS        (WCD937X_BASE_ADDRESS+0x05B)
+#define WCD937X_MBHC_TEST_CTL                       (WCD937X_BASE_ADDRESS+0x05C)
+#define WCD937X_LDOH_MODE                           (WCD937X_BASE_ADDRESS+0x067)
+#define WCD937X_LDOH_BIAS                           (WCD937X_BASE_ADDRESS+0x068)
+#define WCD937X_LDOH_STB_LOADS                      (WCD937X_BASE_ADDRESS+0x069)
+#define WCD937X_LDOH_SLOWRAMP                       (WCD937X_BASE_ADDRESS+0x06A)
+#define WCD937X_MICB1_TEST_CTL_1                    (WCD937X_BASE_ADDRESS+0x06B)
+#define WCD937X_MICB1_TEST_CTL_2                    (WCD937X_BASE_ADDRESS+0x06C)
+#define WCD937X_MICB1_TEST_CTL_3                    (WCD937X_BASE_ADDRESS+0x06D)
+#define WCD937X_MICB2_TEST_CTL_1                    (WCD937X_BASE_ADDRESS+0x06E)
+#define WCD937X_MICB2_TEST_CTL_2                    (WCD937X_BASE_ADDRESS+0x06F)
+#define WCD937X_MICB2_TEST_CTL_3                    (WCD937X_BASE_ADDRESS+0x070)
+#define WCD937X_MICB3_TEST_CTL_1                    (WCD937X_BASE_ADDRESS+0x071)
+#define WCD937X_MICB3_TEST_CTL_2                    (WCD937X_BASE_ADDRESS+0x072)
+#define WCD937X_MICB3_TEST_CTL_3                    (WCD937X_BASE_ADDRESS+0x073)
+#define WCD937X_TX_COM_ADC_VCM                      (WCD937X_BASE_ADDRESS+0x077)
+#define WCD937X_TX_COM_BIAS_ATEST                   (WCD937X_BASE_ADDRESS+0x078)
+#define WCD937X_TX_COM_ADC_INT1_IB                  (WCD937X_BASE_ADDRESS+0x079)
+#define WCD937X_TX_COM_ADC_INT2_IB                  (WCD937X_BASE_ADDRESS+0x07A)
+#define WCD937X_TX_COM_TXFE_DIV_CTL                 (WCD937X_BASE_ADDRESS+0x07B)
+#define WCD937X_TX_COM_TXFE_DIV_START               (WCD937X_BASE_ADDRESS+0x07C)
+#define WCD937X_TX_COM_TXFE_DIV_STOP_9P6M           (WCD937X_BASE_ADDRESS+0x07D)
+#define WCD937X_TX_COM_TXFE_DIV_STOP_12P288M        (WCD937X_BASE_ADDRESS+0x07E)
+#define WCD937X_TX_1_2_TEST_EN                      (WCD937X_BASE_ADDRESS+0x07F)
+#define WCD937X_TX_1_2_ADC_IB                       (WCD937X_BASE_ADDRESS+0x080)
+#define WCD937X_TX_1_2_ATEST_REFCTL                 (WCD937X_BASE_ADDRESS+0x081)
+#define WCD937X_TX_1_2_TEST_CTL                     (WCD937X_BASE_ADDRESS+0x082)
+#define WCD937X_TX_1_2_TEST_BLK_EN                  (WCD937X_BASE_ADDRESS+0x083)
+#define WCD937X_TX_1_2_TXFE_CLKDIV                  (WCD937X_BASE_ADDRESS+0x084)
+#define WCD937X_TX_1_2_SAR2_ERR                     (WCD937X_BASE_ADDRESS+0x085)
+#define WCD937X_TX_1_2_SAR1_ERR                     (WCD937X_BASE_ADDRESS+0x086)
+#define WCD937X_TX_3_TEST_EN                        (WCD937X_BASE_ADDRESS+0x087)
+#define WCD937X_TX_3_ADC_IB                         (WCD937X_BASE_ADDRESS+0x088)
+#define WCD937X_TX_3_ATEST_REFCTL                   (WCD937X_BASE_ADDRESS+0x089)
+#define WCD937X_TX_3_TEST_CTL                       (WCD937X_BASE_ADDRESS+0x08A)
+#define WCD937X_TX_3_TEST_BLK_EN                    (WCD937X_BASE_ADDRESS+0x08B)
+#define WCD937X_TX_3_TXFE_CLKDIV                    (WCD937X_BASE_ADDRESS+0x08C)
+#define WCD937X_TX_3_SPARE_MONO                     (WCD937X_BASE_ADDRESS+0x08D)
+#define WCD937X_TX_3_SAR1_ERR                       (WCD937X_BASE_ADDRESS+0x08E)
+#define WCD937X_CLASSH_MODE_1                       (WCD937X_BASE_ADDRESS+0x097)
+#define WCD937X_CLASSH_MODE_2                       (WCD937X_BASE_ADDRESS+0x098)
+#define WCD937X_CLASSH_MODE_3                       (WCD937X_BASE_ADDRESS+0x099)
+#define WCD937X_CLASSH_CTRL_VCL_1                   (WCD937X_BASE_ADDRESS+0x09A)
+#define WCD937X_CLASSH_CTRL_VCL_2                   (WCD937X_BASE_ADDRESS+0x09B)
+#define WCD937X_CLASSH_CTRL_CCL_1                   (WCD937X_BASE_ADDRESS+0x09C)
+#define WCD937X_CLASSH_CTRL_CCL_2                   (WCD937X_BASE_ADDRESS+0x09D)
+#define WCD937X_CLASSH_CTRL_CCL_3                   (WCD937X_BASE_ADDRESS+0x09E)
+#define WCD937X_CLASSH_CTRL_CCL_4                   (WCD937X_BASE_ADDRESS+0x09F)
+#define WCD937X_CLASSH_CTRL_CCL_5                   (WCD937X_BASE_ADDRESS+0x0A0)
+#define WCD937X_CLASSH_BUCK_TMUX_A_D                (WCD937X_BASE_ADDRESS+0x0A1)
+#define WCD937X_CLASSH_BUCK_SW_DRV_CNTL             (WCD937X_BASE_ADDRESS+0x0A2)
+#define WCD937X_CLASSH_SPARE                        (WCD937X_BASE_ADDRESS+0x0A3)
+#define WCD937X_FLYBACK_EN                          (WCD937X_BASE_ADDRESS+0x0A4)
+#define WCD937X_FLYBACK_VNEG_CTRL_1                 (WCD937X_BASE_ADDRESS+0x0A5)
+#define WCD937X_FLYBACK_VNEG_CTRL_2                 (WCD937X_BASE_ADDRESS+0x0A6)
+#define WCD937X_FLYBACK_VNEG_CTRL_3                 (WCD937X_BASE_ADDRESS+0x0A7)
+#define WCD937X_FLYBACK_VNEG_CTRL_4                 (WCD937X_BASE_ADDRESS+0x0A8)
+#define WCD937X_FLYBACK_VNEG_CTRL_5                 (WCD937X_BASE_ADDRESS+0x0A9)
+#define WCD937X_FLYBACK_VNEG_CTRL_6                 (WCD937X_BASE_ADDRESS+0x0AA)
+#define WCD937X_FLYBACK_VNEG_CTRL_7                 (WCD937X_BASE_ADDRESS+0x0AB)
+#define WCD937X_FLYBACK_VNEG_CTRL_8                 (WCD937X_BASE_ADDRESS+0x0AC)
+#define WCD937X_FLYBACK_VNEG_CTRL_9                 (WCD937X_BASE_ADDRESS+0x0AD)
+#define WCD937X_FLYBACK_VNEGDAC_CTRL_1              (WCD937X_BASE_ADDRESS+0x0AE)
+#define WCD937X_FLYBACK_VNEGDAC_CTRL_2              (WCD937X_BASE_ADDRESS+0x0AF)
+#define WCD937X_FLYBACK_VNEGDAC_CTRL_3              (WCD937X_BASE_ADDRESS+0x0B0)
+#define WCD937X_FLYBACK_CTRL_1                      (WCD937X_BASE_ADDRESS+0x0B1)
+#define WCD937X_FLYBACK_TEST_CTL                    (WCD937X_BASE_ADDRESS+0x0B2)
+#define WCD937X_RX_AUX_SW_CTL                       (WCD937X_BASE_ADDRESS+0x0B3)
+#define WCD937X_RX_PA_AUX_IN_CONN                   (WCD937X_BASE_ADDRESS+0x0B4)
+#define WCD937X_RX_TIMER_DIV                        (WCD937X_BASE_ADDRESS+0x0B5)
+#define WCD937X_RX_OCP_CTL                          (WCD937X_BASE_ADDRESS+0x0B6)
+#define WCD937X_RX_OCP_COUNT                        (WCD937X_BASE_ADDRESS+0x0B7)
+#define WCD937X_RX_BIAS_EAR_DAC                     (WCD937X_BASE_ADDRESS+0x0B8)
+#define WCD937X_RX_BIAS_EAR_AMP                     (WCD937X_BASE_ADDRESS+0x0B9)
+#define WCD937X_RX_BIAS_HPH_LDO                     (WCD937X_BASE_ADDRESS+0x0BA)
+#define WCD937X_RX_BIAS_HPH_PA                      (WCD937X_BASE_ADDRESS+0x0BB)
+#define WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2           (WCD937X_BASE_ADDRESS+0x0BC)
+#define WCD937X_RX_BIAS_HPH_RDAC_LDO                (WCD937X_BASE_ADDRESS+0x0BD)
+#define WCD937X_RX_BIAS_HPH_CNP1                    (WCD937X_BASE_ADDRESS+0x0BE)
+#define WCD937X_RX_BIAS_HPH_LOWPOWER                (WCD937X_BASE_ADDRESS+0x0BF)
+#define WCD937X_RX_BIAS_AUX_DAC                     (WCD937X_BASE_ADDRESS+0x0C0)
+#define WCD937X_RX_BIAS_AUX_AMP                     (WCD937X_BASE_ADDRESS+0x0C1)
+#define WCD937X_RX_BIAS_VNEGDAC_BLEEDER             (WCD937X_BASE_ADDRESS+0x0C2)
+#define WCD937X_RX_BIAS_MISC                        (WCD937X_BASE_ADDRESS+0x0C3)
+#define WCD937X_RX_BIAS_BUCK_RST                    (WCD937X_BASE_ADDRESS+0x0C4)
+#define WCD937X_RX_BIAS_BUCK_VREF_ERRAMP            (WCD937X_BASE_ADDRESS+0x0C5)
+#define WCD937X_RX_BIAS_FLYB_ERRAMP                 (WCD937X_BASE_ADDRESS+0x0C6)
+#define WCD937X_RX_BIAS_FLYB_BUFF                   (WCD937X_BASE_ADDRESS+0x0C7)
+#define WCD937X_RX_BIAS_FLYB_MID_RST                (WCD937X_BASE_ADDRESS+0x0C8)
+#define WCD937X_HPH_L_STATUS                        (WCD937X_BASE_ADDRESS+0x0C9)
+#define WCD937X_HPH_R_STATUS                        (WCD937X_BASE_ADDRESS+0x0CA)
+#define WCD937X_HPH_CNP_EN                          (WCD937X_BASE_ADDRESS+0x0CB)
+#define WCD937X_HPH_CNP_WG_CTL                      (WCD937X_BASE_ADDRESS+0x0CC)
+#define WCD937X_HPH_CNP_WG_TIME                     (WCD937X_BASE_ADDRESS+0x0CD)
+#define WCD937X_HPH_OCP_CTL                         (WCD937X_BASE_ADDRESS+0x0CE)
+#define WCD937X_HPH_AUTO_CHOP                       (WCD937X_BASE_ADDRESS+0x0CF)
+#define WCD937X_HPH_CHOP_CTL                        (WCD937X_BASE_ADDRESS+0x0D0)
+#define WCD937X_HPH_PA_CTL1                         (WCD937X_BASE_ADDRESS+0x0D1)
+#define WCD937X_HPH_PA_CTL2                         (WCD937X_BASE_ADDRESS+0x0D2)
+#define WCD937X_HPH_L_EN                            (WCD937X_BASE_ADDRESS+0x0D3)
+#define WCD937X_HPH_L_TEST                          (WCD937X_BASE_ADDRESS+0x0D4)
+#define WCD937X_HPH_L_ATEST                         (WCD937X_BASE_ADDRESS+0x0D5)
+#define WCD937X_HPH_R_EN                            (WCD937X_BASE_ADDRESS+0x0D6)
+#define WCD937X_HPH_R_TEST                          (WCD937X_BASE_ADDRESS+0x0D7)
+#define WCD937X_HPH_R_ATEST                         (WCD937X_BASE_ADDRESS+0x0D8)
+#define WCD937X_HPH_RDAC_CLK_CTL1                   (WCD937X_BASE_ADDRESS+0x0D9)
+#define WCD937X_HPH_RDAC_CLK_CTL2                   (WCD937X_BASE_ADDRESS+0x0DA)
+#define WCD937X_HPH_RDAC_LDO_CTL                    (WCD937X_BASE_ADDRESS+0x0DB)
+#define WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL            (WCD937X_BASE_ADDRESS+0x0DC)
+#define WCD937X_HPH_REFBUFF_UHQA_CTL                (WCD937X_BASE_ADDRESS+0x0DD)
+#define WCD937X_HPH_REFBUFF_LP_CTL                  (WCD937X_BASE_ADDRESS+0x0DE)
+#define WCD937X_HPH_L_DAC_CTL                       (WCD937X_BASE_ADDRESS+0x0DF)
+#define WCD937X_HPH_R_DAC_CTL                       (WCD937X_BASE_ADDRESS+0x0E0)
+#define WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL      (WCD937X_BASE_ADDRESS+0x0E1)
+#define WCD937X_HPH_SURGE_HPHLR_SURGE_EN            (WCD937X_BASE_ADDRESS+0x0E2)
+#define WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1         (WCD937X_BASE_ADDRESS+0x0E3)
+#define WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS        (WCD937X_BASE_ADDRESS+0x0E4)
+#define WCD937X_EAR_EAR_EN_REG                      (WCD937X_BASE_ADDRESS+0x0E9)
+#define WCD937X_EAR_EAR_PA_CON                      (WCD937X_BASE_ADDRESS+0x0EA)
+#define WCD937X_EAR_EAR_SP_CON                      (WCD937X_BASE_ADDRESS+0x0EB)
+#define WCD937X_EAR_EAR_DAC_CON                     (WCD937X_BASE_ADDRESS+0x0EC)
+#define WCD937X_EAR_EAR_CNP_FSM_CON                 (WCD937X_BASE_ADDRESS+0x0ED)
+#define WCD937X_EAR_TEST_CTL                        (WCD937X_BASE_ADDRESS+0x0EE)
+#define WCD937X_EAR_STATUS_REG_1                    (WCD937X_BASE_ADDRESS+0x0EF)
+#define WCD937X_EAR_STATUS_REG_2                    (WCD937X_BASE_ADDRESS+0x0F0)
+#define WCD937X_ANA_NEW_PAGE_REGISTER               (WCD937X_BASE_ADDRESS+0x100)
+#define WCD937X_HPH_NEW_ANA_HPH2                    (WCD937X_BASE_ADDRESS+0x101)
+#define WCD937X_HPH_NEW_ANA_HPH3                    (WCD937X_BASE_ADDRESS+0x102)
+#define WCD937X_SLEEP_CTL                           (WCD937X_BASE_ADDRESS+0x103)
+#define WCD937X_SLEEP_WATCHDOG_CTL                  (WCD937X_BASE_ADDRESS+0x104)
+#define WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL        (WCD937X_BASE_ADDRESS+0x11F)
+#define WCD937X_MBHC_NEW_CTL_1                      (WCD937X_BASE_ADDRESS+0x120)
+#define WCD937X_MBHC_NEW_CTL_2                      (WCD937X_BASE_ADDRESS+0x121)
+#define WCD937X_MBHC_NEW_PLUG_DETECT_CTL            (WCD937X_BASE_ADDRESS+0x122)
+#define WCD937X_MBHC_NEW_ZDET_ANA_CTL               (WCD937X_BASE_ADDRESS+0x123)
+#define WCD937X_MBHC_NEW_ZDET_RAMP_CTL              (WCD937X_BASE_ADDRESS+0x124)
+#define WCD937X_MBHC_NEW_FSM_STATUS                 (WCD937X_BASE_ADDRESS+0x125)
+#define WCD937X_MBHC_NEW_ADC_RESULT                 (WCD937X_BASE_ADDRESS+0x126)
+#define WCD937X_TX_NEW_TX_CH2_SEL                   (WCD937X_BASE_ADDRESS+0x127)
+#define WCD937X_AUX_AUXPA                           (WCD937X_BASE_ADDRESS+0x128)
+#define WCD937X_LDORXTX_MODE                        (WCD937X_BASE_ADDRESS+0x129)
+#define WCD937X_LDORXTX_CONFIG                      (WCD937X_BASE_ADDRESS+0x12A)
+#define WCD937X_DIE_CRACK_DIE_CRK_DET_EN            (WCD937X_BASE_ADDRESS+0x12C)
+#define WCD937X_DIE_CRACK_DIE_CRK_DET_OUT           (WCD937X_BASE_ADDRESS+0x12D)
+#define WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL           (WCD937X_BASE_ADDRESS+0x132)
+#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L          (WCD937X_BASE_ADDRESS+0x133)
+#define WCD937X_HPH_NEW_INT_RDAC_VREF_CTL           (WCD937X_BASE_ADDRESS+0x134)
+#define WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL       (WCD937X_BASE_ADDRESS+0x135)
+#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R          (WCD937X_BASE_ADDRESS+0x136)
+#define WCD937X_HPH_NEW_INT_PA_MISC1                (WCD937X_BASE_ADDRESS+0x137)
+#define WCD937X_HPH_NEW_INT_PA_MISC2                (WCD937X_BASE_ADDRESS+0x138)
+#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC            (WCD937X_BASE_ADDRESS+0x139)
+#define WCD937X_HPH_NEW_INT_HPH_TIMER1              (WCD937X_BASE_ADDRESS+0x13A)
+#define WCD937X_HPH_NEW_INT_HPH_TIMER2              (WCD937X_BASE_ADDRESS+0x13B)
+#define WCD937X_HPH_NEW_INT_HPH_TIMER3              (WCD937X_BASE_ADDRESS+0x13C)
+#define WCD937X_HPH_NEW_INT_HPH_TIMER4              (WCD937X_BASE_ADDRESS+0x13D)
+#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC2           (WCD937X_BASE_ADDRESS+0x13E)
+#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC3           (WCD937X_BASE_ADDRESS+0x13F)
+#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI     (WCD937X_BASE_ADDRESS+0x145)
+#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP        (WCD937X_BASE_ADDRESS+0x146)
+#define WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP          (WCD937X_BASE_ADDRESS+0x147)
+#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL   (WCD937X_BASE_ADDRESS+0x1AF)
+#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL \
+						    (WCD937X_BASE_ADDRESS+0x1B0)
+#define WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT       (WCD937X_BASE_ADDRESS+0x1B1)
+#define WCD937X_MBHC_NEW_INT_SPARE_2                (WCD937X_BASE_ADDRESS+0x1B2)
+#define WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON         (WCD937X_BASE_ADDRESS+0x1B7)
+#define WCD937X_EAR_INT_NEW_CNP_VCM_CON1            (WCD937X_BASE_ADDRESS+0x1B8)
+#define WCD937X_EAR_INT_NEW_CNP_VCM_CON2            (WCD937X_BASE_ADDRESS+0x1B9)
+#define WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS        (WCD937X_BASE_ADDRESS+0x1BA)
+#define WCD937X_AUX_INT_EN_REG                      (WCD937X_BASE_ADDRESS+0x1BD)
+#define WCD937X_AUX_INT_PA_CTRL                     (WCD937X_BASE_ADDRESS+0x1BE)
+#define WCD937X_AUX_INT_SP_CTRL                     (WCD937X_BASE_ADDRESS+0x1BF)
+#define WCD937X_AUX_INT_DAC_CTRL                    (WCD937X_BASE_ADDRESS+0x1C0)
+#define WCD937X_AUX_INT_CLK_CTRL                    (WCD937X_BASE_ADDRESS+0x1C1)
+#define WCD937X_AUX_INT_TEST_CTRL                   (WCD937X_BASE_ADDRESS+0x1C2)
+#define WCD937X_AUX_INT_STATUS_REG                  (WCD937X_BASE_ADDRESS+0x1C3)
+#define WCD937X_AUX_INT_MISC                        (WCD937X_BASE_ADDRESS+0x1C4)
+#define WCD937X_LDORXTX_INT_BIAS                    (WCD937X_BASE_ADDRESS+0x1C5)
+#define WCD937X_LDORXTX_INT_STB_LOADS_DTEST         (WCD937X_BASE_ADDRESS+0x1C6)
+#define WCD937X_LDORXTX_INT_TEST0                   (WCD937X_BASE_ADDRESS+0x1C7)
+#define WCD937X_LDORXTX_INT_STARTUP_TIMER           (WCD937X_BASE_ADDRESS+0x1C8)
+#define WCD937X_LDORXTX_INT_TEST1                   (WCD937X_BASE_ADDRESS+0x1C9)
+#define WCD937X_LDORXTX_INT_STATUS                  (WCD937X_BASE_ADDRESS+0x1CA)
+#define WCD937X_SLEEP_INT_WATCHDOG_CTL_1            (WCD937X_BASE_ADDRESS+0x1D0)
+#define WCD937X_SLEEP_INT_WATCHDOG_CTL_2            (WCD937X_BASE_ADDRESS+0x1D1)
+#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1      (WCD937X_BASE_ADDRESS+0x1D3)
+#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2      (WCD937X_BASE_ADDRESS+0x1D4)
+#define WCD937X_DIGITAL_PAGE_REGISTER               (WCD937X_BASE_ADDRESS+0x400)
+#define WCD937X_DIGITAL_CHIP_ID0                    (WCD937X_BASE_ADDRESS+0x401)
+#define WCD937X_DIGITAL_CHIP_ID1                    (WCD937X_BASE_ADDRESS+0x402)
+#define WCD937X_DIGITAL_CHIP_ID2                    (WCD937X_BASE_ADDRESS+0x403)
+#define WCD937X_DIGITAL_CHIP_ID3                    (WCD937X_BASE_ADDRESS+0x404)
+#define WCD937X_DIGITAL_CDC_RST_CTL                 (WCD937X_BASE_ADDRESS+0x406)
+#define WCD937X_DIGITAL_TOP_CLK_CFG                 (WCD937X_BASE_ADDRESS+0x407)
+#define WCD937X_DIGITAL_CDC_ANA_CLK_CTL             (WCD937X_BASE_ADDRESS+0x408)
+#define WCD937X_DIGITAL_CDC_DIG_CLK_CTL             (WCD937X_BASE_ADDRESS+0x409)
+#define WCD937X_DIGITAL_SWR_RST_EN                  (WCD937X_BASE_ADDRESS+0x40A)
+#define WCD937X_DIGITAL_CDC_PATH_MODE               (WCD937X_BASE_ADDRESS+0x40B)
+#define WCD937X_DIGITAL_CDC_RX_RST                  (WCD937X_BASE_ADDRESS+0x40C)
+#define WCD937X_DIGITAL_CDC_RX0_CTL                 (WCD937X_BASE_ADDRESS+0x40D)
+#define WCD937X_DIGITAL_CDC_RX1_CTL                 (WCD937X_BASE_ADDRESS+0x40E)
+#define WCD937X_DIGITAL_CDC_RX2_CTL                 (WCD937X_BASE_ADDRESS+0x40F)
+#define WCD937X_DIGITAL_DEM_BYPASS_DATA0            (WCD937X_BASE_ADDRESS+0x410)
+#define WCD937X_DIGITAL_DEM_BYPASS_DATA1            (WCD937X_BASE_ADDRESS+0x411)
+#define WCD937X_DIGITAL_DEM_BYPASS_DATA2            (WCD937X_BASE_ADDRESS+0x412)
+#define WCD937X_DIGITAL_DEM_BYPASS_DATA3            (WCD937X_BASE_ADDRESS+0x413)
+#define WCD937X_DIGITAL_CDC_COMP_CTL_0              (WCD937X_BASE_ADDRESS+0x414)
+#define WCD937X_DIGITAL_CDC_RX_DELAY_CTL            (WCD937X_BASE_ADDRESS+0x417)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_0            (WCD937X_BASE_ADDRESS+0x418)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_1            (WCD937X_BASE_ADDRESS+0x419)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_0            (WCD937X_BASE_ADDRESS+0x41A)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_1            (WCD937X_BASE_ADDRESS+0x41B)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_0            (WCD937X_BASE_ADDRESS+0x41C)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_1            (WCD937X_BASE_ADDRESS+0x41D)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_0            (WCD937X_BASE_ADDRESS+0x41E)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_1            (WCD937X_BASE_ADDRESS+0x41F)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_0            (WCD937X_BASE_ADDRESS+0x420)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_1            (WCD937X_BASE_ADDRESS+0x421)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A6_0            (WCD937X_BASE_ADDRESS+0x422)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_A7_0            (WCD937X_BASE_ADDRESS+0x423)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_C_0             (WCD937X_BASE_ADDRESS+0x424)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_C_1             (WCD937X_BASE_ADDRESS+0x425)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_C_2             (WCD937X_BASE_ADDRESS+0x426)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_C_3             (WCD937X_BASE_ADDRESS+0x427)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R1              (WCD937X_BASE_ADDRESS+0x428)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R2              (WCD937X_BASE_ADDRESS+0x429)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R3              (WCD937X_BASE_ADDRESS+0x42A)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R4              (WCD937X_BASE_ADDRESS+0x42B)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R5              (WCD937X_BASE_ADDRESS+0x42C)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R6              (WCD937X_BASE_ADDRESS+0x42D)
+#define WCD937X_DIGITAL_CDC_HPH_DSM_R7              (WCD937X_BASE_ADDRESS+0x42E)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_0            (WCD937X_BASE_ADDRESS+0x42F)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_1            (WCD937X_BASE_ADDRESS+0x430)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_0            (WCD937X_BASE_ADDRESS+0x431)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_1            (WCD937X_BASE_ADDRESS+0x432)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_0            (WCD937X_BASE_ADDRESS+0x433)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_1            (WCD937X_BASE_ADDRESS+0x434)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_0            (WCD937X_BASE_ADDRESS+0x435)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_1            (WCD937X_BASE_ADDRESS+0x436)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_0            (WCD937X_BASE_ADDRESS+0x437)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_1            (WCD937X_BASE_ADDRESS+0x438)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A6_0            (WCD937X_BASE_ADDRESS+0x439)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_A7_0            (WCD937X_BASE_ADDRESS+0x43A)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_C_0             (WCD937X_BASE_ADDRESS+0x43B)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_C_1             (WCD937X_BASE_ADDRESS+0x43C)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_C_2             (WCD937X_BASE_ADDRESS+0x43D)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_C_3             (WCD937X_BASE_ADDRESS+0x43E)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R1              (WCD937X_BASE_ADDRESS+0x43F)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R2              (WCD937X_BASE_ADDRESS+0x440)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R3              (WCD937X_BASE_ADDRESS+0x441)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R4              (WCD937X_BASE_ADDRESS+0x442)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R5              (WCD937X_BASE_ADDRESS+0x443)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R6              (WCD937X_BASE_ADDRESS+0x444)
+#define WCD937X_DIGITAL_CDC_AUX_DSM_R7              (WCD937X_BASE_ADDRESS+0x445)
+#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0           (WCD937X_BASE_ADDRESS+0x446)
+#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1           (WCD937X_BASE_ADDRESS+0x447)
+#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0          (WCD937X_BASE_ADDRESS+0x448)
+#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1          (WCD937X_BASE_ADDRESS+0x449)
+#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2          (WCD937X_BASE_ADDRESS+0x44A)
+#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0          (WCD937X_BASE_ADDRESS+0x44B)
+#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1          (WCD937X_BASE_ADDRESS+0x44C)
+#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2          (WCD937X_BASE_ADDRESS+0x44D)
+#define WCD937X_DIGITAL_CDC_HPH_GAIN_CTL            (WCD937X_BASE_ADDRESS+0x44E)
+#define WCD937X_DIGITAL_CDC_AUX_GAIN_CTL            (WCD937X_BASE_ADDRESS+0x44F)
+#define WCD937X_DIGITAL_CDC_EAR_PATH_CTL            (WCD937X_BASE_ADDRESS+0x450)
+#define WCD937X_DIGITAL_CDC_SWR_CLH                 (WCD937X_BASE_ADDRESS+0x451)
+#define WCD937X_DIGITAL_SWR_CLH_BYP                 (WCD937X_BASE_ADDRESS+0x452)
+#define WCD937X_DIGITAL_CDC_TX0_CTL                 (WCD937X_BASE_ADDRESS+0x453)
+#define WCD937X_DIGITAL_CDC_TX1_CTL                 (WCD937X_BASE_ADDRESS+0x454)
+#define WCD937X_DIGITAL_CDC_TX2_CTL                 (WCD937X_BASE_ADDRESS+0x455)
+#define WCD937X_DIGITAL_CDC_TX_RST                  (WCD937X_BASE_ADDRESS+0x456)
+#define WCD937X_DIGITAL_CDC_REQ_CTL                 (WCD937X_BASE_ADDRESS+0x457)
+#define WCD937X_DIGITAL_CDC_AMIC_CTL                (WCD937X_BASE_ADDRESS+0x45A)
+#define WCD937X_DIGITAL_CDC_DMIC_CTL                (WCD937X_BASE_ADDRESS+0x45B)
+#define WCD937X_DIGITAL_CDC_DMIC0_CTL               (WCD937X_BASE_ADDRESS+0x45C)
+#define WCD937X_DIGITAL_CDC_DMIC1_CTL               (WCD937X_BASE_ADDRESS+0x45D)
+#define WCD937X_DIGITAL_CDC_DMIC2_CTL               (WCD937X_BASE_ADDRESS+0x45E)
+#define WCD937X_DIGITAL_EFUSE_CTL                   (WCD937X_BASE_ADDRESS+0x45F)
+#define WCD937X_DIGITAL_EFUSE_PRG_CTL               (WCD937X_BASE_ADDRESS+0x460)
+#define WCD937X_DIGITAL_EFUSE_TEST_CTL_0            (WCD937X_BASE_ADDRESS+0x461)
+#define WCD937X_DIGITAL_EFUSE_TEST_CTL_1            (WCD937X_BASE_ADDRESS+0x462)
+#define WCD937X_DIGITAL_EFUSE_T_DATA_0              (WCD937X_BASE_ADDRESS+0x463)
+#define WCD937X_DIGITAL_EFUSE_T_DATA_1              (WCD937X_BASE_ADDRESS+0x464)
+#define WCD937X_DIGITAL_PDM_WD_CTL0                 (WCD937X_BASE_ADDRESS+0x465)
+#define WCD937X_DIGITAL_PDM_WD_CTL1                 (WCD937X_BASE_ADDRESS+0x466)
+#define WCD937X_DIGITAL_PDM_WD_CTL2                 (WCD937X_BASE_ADDRESS+0x467)
+#define WCD937X_DIGITAL_INTR_MODE                   (WCD937X_BASE_ADDRESS+0x46A)
+#define WCD937X_DIGITAL_INTR_MASK_0                 (WCD937X_BASE_ADDRESS+0x46B)
+#define WCD937X_DIGITAL_INTR_MASK_1                 (WCD937X_BASE_ADDRESS+0x46C)
+#define WCD937X_DIGITAL_INTR_MASK_2                 (WCD937X_BASE_ADDRESS+0x46D)
+#define WCD937X_DIGITAL_INTR_STATUS_0               (WCD937X_BASE_ADDRESS+0x46E)
+#define WCD937X_DIGITAL_INTR_STATUS_1               (WCD937X_BASE_ADDRESS+0x46F)
+#define WCD937X_DIGITAL_INTR_STATUS_2               (WCD937X_BASE_ADDRESS+0x470)
+#define WCD937X_DIGITAL_INTR_CLEAR_0                (WCD937X_BASE_ADDRESS+0x471)
+#define WCD937X_DIGITAL_INTR_CLEAR_1                (WCD937X_BASE_ADDRESS+0x472)
+#define WCD937X_DIGITAL_INTR_CLEAR_2                (WCD937X_BASE_ADDRESS+0x473)
+#define WCD937X_DIGITAL_INTR_LEVEL_0                (WCD937X_BASE_ADDRESS+0x474)
+#define WCD937X_DIGITAL_INTR_LEVEL_1                (WCD937X_BASE_ADDRESS+0x475)
+#define WCD937X_DIGITAL_INTR_LEVEL_2                (WCD937X_BASE_ADDRESS+0x476)
+#define WCD937X_DIGITAL_INTR_SET_0                  (WCD937X_BASE_ADDRESS+0x477)
+#define WCD937X_DIGITAL_INTR_SET_1                  (WCD937X_BASE_ADDRESS+0x478)
+#define WCD937X_DIGITAL_INTR_SET_2                  (WCD937X_BASE_ADDRESS+0x479)
+#define WCD937X_DIGITAL_INTR_TEST_0                 (WCD937X_BASE_ADDRESS+0x47A)
+#define WCD937X_DIGITAL_INTR_TEST_1                 (WCD937X_BASE_ADDRESS+0x47B)
+#define WCD937X_DIGITAL_INTR_TEST_2                 (WCD937X_BASE_ADDRESS+0x47C)
+#define WCD937X_DIGITAL_CDC_CONN_RX0_CTL            (WCD937X_BASE_ADDRESS+0x47F)
+#define WCD937X_DIGITAL_CDC_CONN_RX1_CTL            (WCD937X_BASE_ADDRESS+0x480)
+#define WCD937X_DIGITAL_CDC_CONN_RX2_CTL            (WCD937X_BASE_ADDRESS+0x481)
+#define WCD937X_DIGITAL_CDC_CONN_TX_CTL             (WCD937X_BASE_ADDRESS+0x482)
+#define WCD937X_DIGITAL_LOOP_BACK_MODE              (WCD937X_BASE_ADDRESS+0x483)
+#define WCD937X_DIGITAL_SWR_DAC_TEST                (WCD937X_BASE_ADDRESS+0x484)
+#define WCD937X_DIGITAL_SWR_HM_TEST_RX_0            (WCD937X_BASE_ADDRESS+0x485)
+#define WCD937X_DIGITAL_SWR_HM_TEST_TX_0            (WCD937X_BASE_ADDRESS+0x491)
+#define WCD937X_DIGITAL_SWR_HM_TEST_RX_1            (WCD937X_BASE_ADDRESS+0x492)
+#define WCD937X_DIGITAL_SWR_HM_TEST_TX_1            (WCD937X_BASE_ADDRESS+0x493)
+#define WCD937X_DIGITAL_SWR_HM_TEST                 (WCD937X_BASE_ADDRESS+0x494)
+#define WCD937X_DIGITAL_PAD_CTL_PDM_RX0             (WCD937X_BASE_ADDRESS+0x495)
+#define WCD937X_DIGITAL_PAD_CTL_PDM_RX1             (WCD937X_BASE_ADDRESS+0x496)
+#define WCD937X_DIGITAL_PAD_CTL_PDM_RX2             (WCD937X_BASE_ADDRESS+0x497)
+#define WCD937X_DIGITAL_PAD_CTL_PDM_TX              (WCD937X_BASE_ADDRESS+0x498)
+#define WCD937X_DIGITAL_PAD_INP_DIS_0               (WCD937X_BASE_ADDRESS+0x499)
+#define WCD937X_DIGITAL_PAD_INP_DIS_1               (WCD937X_BASE_ADDRESS+0x49A)
+#define WCD937X_DIGITAL_DRIVE_STRENGTH_0            (WCD937X_BASE_ADDRESS+0x49B)
+#define WCD937X_DIGITAL_DRIVE_STRENGTH_1            (WCD937X_BASE_ADDRESS+0x49C)
+#define WCD937X_DIGITAL_DRIVE_STRENGTH_2            (WCD937X_BASE_ADDRESS+0x49D)
+#define WCD937X_DIGITAL_RX_DATA_EDGE_CTL            (WCD937X_BASE_ADDRESS+0x49E)
+#define WCD937X_DIGITAL_TX_DATA_EDGE_CTL            (WCD937X_BASE_ADDRESS+0x49F)
+#define WCD937X_DIGITAL_GPIO_MODE                   (WCD937X_BASE_ADDRESS+0x4A0)
+#define WCD937X_DIGITAL_PIN_CTL_OE                  (WCD937X_BASE_ADDRESS+0x4A1)
+#define WCD937X_DIGITAL_PIN_CTL_DATA_0              (WCD937X_BASE_ADDRESS+0x4A2)
+#define WCD937X_DIGITAL_PIN_CTL_DATA_1              (WCD937X_BASE_ADDRESS+0x4A3)
+#define WCD937X_DIGITAL_PIN_STATUS_0                (WCD937X_BASE_ADDRESS+0x4A4)
+#define WCD937X_DIGITAL_PIN_STATUS_1                (WCD937X_BASE_ADDRESS+0x4A5)
+#define WCD937X_DIGITAL_DIG_DEBUG_CTL               (WCD937X_BASE_ADDRESS+0x4A6)
+#define WCD937X_DIGITAL_DIG_DEBUG_EN                (WCD937X_BASE_ADDRESS+0x4A7)
+#define WCD937X_DIGITAL_ANA_CSR_DBG_ADD             (WCD937X_BASE_ADDRESS+0x4A8)
+#define WCD937X_DIGITAL_ANA_CSR_DBG_CTL             (WCD937X_BASE_ADDRESS+0x4A9)
+#define WCD937X_DIGITAL_SSP_DBG                     (WCD937X_BASE_ADDRESS+0x4AA)
+#define WCD937X_DIGITAL_MODE_STATUS_0               (WCD937X_BASE_ADDRESS+0x4AB)
+#define WCD937X_DIGITAL_MODE_STATUS_1               (WCD937X_BASE_ADDRESS+0x4AC)
+#define WCD937X_DIGITAL_SPARE_0                     (WCD937X_BASE_ADDRESS+0x4AD)
+#define WCD937X_DIGITAL_SPARE_1                     (WCD937X_BASE_ADDRESS+0x4AE)
+#define WCD937X_DIGITAL_SPARE_2                     (WCD937X_BASE_ADDRESS+0x4AF)
+#define WCD937X_DIGITAL_EFUSE_REG_0                 (WCD937X_BASE_ADDRESS+0x4B0)
+#define WCD937X_DIGITAL_EFUSE_REG_1                 (WCD937X_BASE_ADDRESS+0x4B1)
+#define WCD937X_DIGITAL_EFUSE_REG_2                 (WCD937X_BASE_ADDRESS+0x4B2)
+#define WCD937X_DIGITAL_EFUSE_REG_3                 (WCD937X_BASE_ADDRESS+0x4B3)
+#define WCD937X_DIGITAL_EFUSE_REG_4                 (WCD937X_BASE_ADDRESS+0x4B4)
+#define WCD937X_DIGITAL_EFUSE_REG_5                 (WCD937X_BASE_ADDRESS+0x4B5)
+#define WCD937X_DIGITAL_EFUSE_REG_6                 (WCD937X_BASE_ADDRESS+0x4B6)
+#define WCD937X_DIGITAL_EFUSE_REG_7                 (WCD937X_BASE_ADDRESS+0x4B7)
+#define WCD937X_DIGITAL_EFUSE_REG_8                 (WCD937X_BASE_ADDRESS+0x4B8)
+#define WCD937X_DIGITAL_EFUSE_REG_9                 (WCD937X_BASE_ADDRESS+0x4B9)
+#define WCD937X_DIGITAL_EFUSE_REG_10                (WCD937X_BASE_ADDRESS+0x4BA)
+#define WCD937X_DIGITAL_EFUSE_REG_11                (WCD937X_BASE_ADDRESS+0x4BB)
+#define WCD937X_DIGITAL_EFUSE_REG_12                (WCD937X_BASE_ADDRESS+0x4BC)
+#define WCD937X_DIGITAL_EFUSE_REG_13                (WCD937X_BASE_ADDRESS+0x4BD)
+#define WCD937X_DIGITAL_EFUSE_REG_14                (WCD937X_BASE_ADDRESS+0x4BE)
+#define WCD937X_DIGITAL_EFUSE_REG_15                (WCD937X_BASE_ADDRESS+0x4BF)
+#define WCD937X_DIGITAL_EFUSE_REG_16                (WCD937X_BASE_ADDRESS+0x4C0)
+#define WCD937X_DIGITAL_EFUSE_REG_17                (WCD937X_BASE_ADDRESS+0x4C1)
+#define WCD937X_DIGITAL_EFUSE_REG_18                (WCD937X_BASE_ADDRESS+0x4C2)
+#define WCD937X_DIGITAL_EFUSE_REG_19                (WCD937X_BASE_ADDRESS+0x4C3)
+#define WCD937X_DIGITAL_EFUSE_REG_20                (WCD937X_BASE_ADDRESS+0x4C4)
+#define WCD937X_DIGITAL_EFUSE_REG_21                (WCD937X_BASE_ADDRESS+0x4C5)
+#define WCD937X_DIGITAL_EFUSE_REG_22                (WCD937X_BASE_ADDRESS+0x4C6)
+#define WCD937X_DIGITAL_EFUSE_REG_23                (WCD937X_BASE_ADDRESS+0x4C7)
+#define WCD937X_DIGITAL_EFUSE_REG_24                (WCD937X_BASE_ADDRESS+0x4C8)
+#define WCD937X_DIGITAL_EFUSE_REG_25                (WCD937X_BASE_ADDRESS+0x4C9)
+#define WCD937X_DIGITAL_EFUSE_REG_26                (WCD937X_BASE_ADDRESS+0x4CA)
+#define WCD937X_DIGITAL_EFUSE_REG_27                (WCD937X_BASE_ADDRESS+0x4CB)
+#define WCD937X_DIGITAL_EFUSE_REG_28                (WCD937X_BASE_ADDRESS+0x4CC)
+#define WCD937X_DIGITAL_EFUSE_REG_29                (WCD937X_BASE_ADDRESS+0x4CD)
+#define WCD937X_DIGITAL_EFUSE_REG_30                (WCD937X_BASE_ADDRESS+0x4CE)
+#define WCD937X_DIGITAL_EFUSE_REG_31                (WCD937X_BASE_ADDRESS+0x4CF)
+
+#define WCD937X_REGISTERS_MAX_SIZE (WCD937X_BASE_ADDRESS+0x4D0)
+#define WCD937X_MAX_REGISTER (WCD937X_REGISTERS_MAX_SIZE - 1)
+
+#endif

+ 462 - 0
asoc/codecs/wcd937x/wcd937x-regmap.c

@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd937x-registers.h"
+
+extern const u8 wcd937x_reg_access[WCD937X_REGISTERS_MAX_SIZE];
+
+static const struct reg_default wcd937x_defaults[] = {
+	{ WCD937X_ANA_BIAS,                      0x00 },
+	{ WCD937X_ANA_RX_SUPPLIES,               0x00 },
+	{ WCD937X_ANA_HPH,                       0x0C },
+	{ WCD937X_ANA_EAR,                       0x00 },
+	{ WCD937X_ANA_EAR_COMPANDER_CTL,         0x02 },
+	{ WCD937X_ANA_TX_CH1,                    0x20 },
+	{ WCD937X_ANA_TX_CH2,                    0x00 },
+	{ WCD937X_ANA_TX_CH3,                    0x20 },
+	{ WCD937X_ANA_TX_CH3_HPF,                0x00 },
+	{ WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC,  0x00 },
+	{ WCD937X_ANA_MICB3_DSP_EN_LOGIC,        0x00 },
+	{ WCD937X_ANA_MBHC_MECH,                 0x39 },
+	{ WCD937X_ANA_MBHC_ELECT,                0x08 },
+	{ WCD937X_ANA_MBHC_ZDET,                 0x00 },
+	{ WCD937X_ANA_MBHC_RESULT_1,             0x00 },
+	{ WCD937X_ANA_MBHC_RESULT_2,             0x00 },
+	{ WCD937X_ANA_MBHC_RESULT_3,             0x00 },
+	{ WCD937X_ANA_MBHC_BTN0,                 0x00 },
+	{ WCD937X_ANA_MBHC_BTN1,                 0x10 },
+	{ WCD937X_ANA_MBHC_BTN2,                 0x20 },
+	{ WCD937X_ANA_MBHC_BTN3,                 0x30 },
+	{ WCD937X_ANA_MBHC_BTN4,                 0x40 },
+	{ WCD937X_ANA_MBHC_BTN5,                 0x50 },
+	{ WCD937X_ANA_MBHC_BTN6,                 0x60 },
+	{ WCD937X_ANA_MBHC_BTN7,                 0x70 },
+	{ WCD937X_ANA_MICB1,                     0x10 },
+	{ WCD937X_ANA_MICB2,                     0x10 },
+	{ WCD937X_ANA_MICB2_RAMP,                0x00 },
+	{ WCD937X_ANA_MICB3,                     0x10 },
+	{ WCD937X_BIAS_CTL,                      0x2A },
+	{ WCD937X_BIAS_VBG_FINE_ADJ,             0x55 },
+	{ WCD937X_LDOL_VDDCX_ADJUST,             0x01 },
+	{ WCD937X_LDOL_DISABLE_LDOL,             0x00 },
+	{ WCD937X_MBHC_CTL_CLK,                  0x00 },
+	{ WCD937X_MBHC_CTL_ANA,                  0x00 },
+	{ WCD937X_MBHC_CTL_SPARE_1,              0x00 },
+	{ WCD937X_MBHC_CTL_SPARE_2,              0x00 },
+	{ WCD937X_MBHC_CTL_BCS,                  0x00 },
+	{ WCD937X_MBHC_MOISTURE_DET_FSM_STATUS,  0x00 },
+	{ WCD937X_MBHC_TEST_CTL,                 0x00 },
+	{ WCD937X_LDOH_MODE,                     0x2B },
+	{ WCD937X_LDOH_BIAS,                     0x68 },
+	{ WCD937X_LDOH_STB_LOADS,                0x00 },
+	{ WCD937X_LDOH_SLOWRAMP,                 0x50 },
+	{ WCD937X_MICB1_TEST_CTL_1,              0x1A },
+	{ WCD937X_MICB1_TEST_CTL_2,              0x18 },
+	{ WCD937X_MICB1_TEST_CTL_3,              0xA4 },
+	{ WCD937X_MICB2_TEST_CTL_1,              0x1A },
+	{ WCD937X_MICB2_TEST_CTL_2,              0x18 },
+	{ WCD937X_MICB2_TEST_CTL_3,              0xA4 },
+	{ WCD937X_MICB3_TEST_CTL_1,              0x1A },
+	{ WCD937X_MICB3_TEST_CTL_2,              0x18 },
+	{ WCD937X_MICB3_TEST_CTL_3,              0xA4 },
+	{ WCD937X_TX_COM_ADC_VCM,                0x39 },
+	{ WCD937X_TX_COM_BIAS_ATEST,             0xC0 },
+	{ WCD937X_TX_COM_ADC_INT1_IB,            0x6F },
+	{ WCD937X_TX_COM_ADC_INT2_IB,            0x4F },
+	{ WCD937X_TX_COM_TXFE_DIV_CTL,           0x2E },
+	{ WCD937X_TX_COM_TXFE_DIV_START,         0x00 },
+	{ WCD937X_TX_COM_TXFE_DIV_STOP_9P6M,     0xC7 },
+	{ WCD937X_TX_COM_TXFE_DIV_STOP_12P288M,  0xFF },
+	{ WCD937X_TX_1_2_TEST_EN,                0xCC },
+	{ WCD937X_TX_1_2_ADC_IB,                 0x09 },
+	{ WCD937X_TX_1_2_ATEST_REFCTL,           0x0A },
+	{ WCD937X_TX_1_2_TEST_CTL,               0x38 },
+	{ WCD937X_TX_1_2_TEST_BLK_EN,            0xFF },
+	{ WCD937X_TX_1_2_TXFE_CLKDIV,            0x00 },
+	{ WCD937X_TX_1_2_SAR2_ERR,               0x00 },
+	{ WCD937X_TX_1_2_SAR1_ERR,               0x00 },
+	{ WCD937X_TX_3_TEST_EN,                  0xCC },
+	{ WCD937X_TX_3_ADC_IB,                   0x09 },
+	{ WCD937X_TX_3_ATEST_REFCTL,             0x0A },
+	{ WCD937X_TX_3_TEST_CTL,                 0x38 },
+	{ WCD937X_TX_3_TEST_BLK_EN,              0xFF },
+	{ WCD937X_TX_3_TXFE_CLKDIV,              0x00 },
+	{ WCD937X_TX_3_SPARE_MONO,               0x00 },
+	{ WCD937X_TX_3_SAR1_ERR,                 0x00 },
+	{ WCD937X_CLASSH_MODE_1,                 0x40 },
+	{ WCD937X_CLASSH_MODE_2,                 0x3A },
+	{ WCD937X_CLASSH_MODE_3,                 0x00 },
+	{ WCD937X_CLASSH_CTRL_VCL_1,             0x70 },
+	{ WCD937X_CLASSH_CTRL_VCL_2,             0x82 },
+	{ WCD937X_CLASSH_CTRL_CCL_1,             0x31 },
+	{ WCD937X_CLASSH_CTRL_CCL_2,             0x80 },
+	{ WCD937X_CLASSH_CTRL_CCL_3,             0x80 },
+	{ WCD937X_CLASSH_CTRL_CCL_4,             0x51 },
+	{ WCD937X_CLASSH_CTRL_CCL_5,             0x00 },
+	{ WCD937X_CLASSH_BUCK_TMUX_A_D,          0x00 },
+	{ WCD937X_CLASSH_BUCK_SW_DRV_CNTL,       0x77 },
+	{ WCD937X_CLASSH_SPARE,                  0x00 },
+	{ WCD937X_FLYBACK_EN,                    0x4E },
+	{ WCD937X_FLYBACK_VNEG_CTRL_1,           0x0B },
+	{ WCD937X_FLYBACK_VNEG_CTRL_2,           0x45 },
+	{ WCD937X_FLYBACK_VNEG_CTRL_3,           0x74 },
+	{ WCD937X_FLYBACK_VNEG_CTRL_4,           0x7F },
+	{ WCD937X_FLYBACK_VNEG_CTRL_5,           0x83 },
+	{ WCD937X_FLYBACK_VNEG_CTRL_6,           0x98 },
+	{ WCD937X_FLYBACK_VNEG_CTRL_7,           0xA9 },
+	{ WCD937X_FLYBACK_VNEG_CTRL_8,           0x68 },
+	{ WCD937X_FLYBACK_VNEG_CTRL_9,           0x64 },
+	{ WCD937X_FLYBACK_VNEGDAC_CTRL_1,        0xED },
+	{ WCD937X_FLYBACK_VNEGDAC_CTRL_2,        0xF0 },
+	{ WCD937X_FLYBACK_VNEGDAC_CTRL_3,        0xA6 },
+	{ WCD937X_FLYBACK_CTRL_1,                0x65 },
+	{ WCD937X_FLYBACK_TEST_CTL,              0x00 },
+	{ WCD937X_RX_AUX_SW_CTL,                 0x00 },
+	{ WCD937X_RX_PA_AUX_IN_CONN,             0x00 },
+	{ WCD937X_RX_TIMER_DIV,                  0x32 },
+	{ WCD937X_RX_OCP_CTL,                    0x1F },
+	{ WCD937X_RX_OCP_COUNT,                  0x77 },
+	{ WCD937X_RX_BIAS_EAR_DAC,               0xA0 },
+	{ WCD937X_RX_BIAS_EAR_AMP,               0xAA },
+	{ WCD937X_RX_BIAS_HPH_LDO,               0xA9 },
+	{ WCD937X_RX_BIAS_HPH_PA,                0xAA },
+	{ WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2,     0x8A },
+	{ WCD937X_RX_BIAS_HPH_RDAC_LDO,          0x88 },
+	{ WCD937X_RX_BIAS_HPH_CNP1,              0x82 },
+	{ WCD937X_RX_BIAS_HPH_LOWPOWER,          0x82 },
+	{ WCD937X_RX_BIAS_AUX_DAC,               0xA0 },
+	{ WCD937X_RX_BIAS_AUX_AMP,               0xAA },
+	{ WCD937X_RX_BIAS_VNEGDAC_BLEEDER,       0x50 },
+	{ WCD937X_RX_BIAS_MISC,                  0x00 },
+	{ WCD937X_RX_BIAS_BUCK_RST,              0x08 },
+	{ WCD937X_RX_BIAS_BUCK_VREF_ERRAMP,      0x44 },
+	{ WCD937X_RX_BIAS_FLYB_ERRAMP,           0x40 },
+	{ WCD937X_RX_BIAS_FLYB_BUFF,             0xAA },
+	{ WCD937X_RX_BIAS_FLYB_MID_RST,          0x14 },
+	{ WCD937X_HPH_L_STATUS,                  0x04 },
+	{ WCD937X_HPH_R_STATUS,                  0x04 },
+	{ WCD937X_HPH_CNP_EN,                    0x80 },
+	{ WCD937X_HPH_CNP_WG_CTL,                0x9A },
+	{ WCD937X_HPH_CNP_WG_TIME,               0x14 },
+	{ WCD937X_HPH_OCP_CTL,                   0x28 },
+	{ WCD937X_HPH_AUTO_CHOP,                 0x16 },
+	{ WCD937X_HPH_CHOP_CTL,                  0x83 },
+	{ WCD937X_HPH_PA_CTL1,                   0x46 },
+	{ WCD937X_HPH_PA_CTL2,                   0x50 },
+	{ WCD937X_HPH_L_EN,                      0x80 },
+	{ WCD937X_HPH_L_TEST,                    0xE0 },
+	{ WCD937X_HPH_L_ATEST,                   0x50 },
+	{ WCD937X_HPH_R_EN,                      0x80 },
+	{ WCD937X_HPH_R_TEST,                    0xE0 },
+	{ WCD937X_HPH_R_ATEST,                   0x54 },
+	{ WCD937X_HPH_RDAC_CLK_CTL1,             0x99 },
+	{ WCD937X_HPH_RDAC_CLK_CTL2,             0x9B },
+	{ WCD937X_HPH_RDAC_LDO_CTL,              0x33 },
+	{ WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL,      0x00 },
+	{ WCD937X_HPH_REFBUFF_UHQA_CTL,          0xA8 },
+	{ WCD937X_HPH_REFBUFF_LP_CTL,            0x0E },
+	{ WCD937X_HPH_L_DAC_CTL,                 0x20 },
+	{ WCD937X_HPH_R_DAC_CTL,                 0x20 },
+	{ WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55 },
+	{ WCD937X_HPH_SURGE_HPHLR_SURGE_EN,      0x19 },
+	{ WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1,   0xA0 },
+	{ WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS,  0x00 },
+	{ WCD937X_EAR_EAR_EN_REG,                0x22 },
+	{ WCD937X_EAR_EAR_PA_CON,                0x44 },
+	{ WCD937X_EAR_EAR_SP_CON,                0xDB },
+	{ WCD937X_EAR_EAR_DAC_CON,               0x80 },
+	{ WCD937X_EAR_EAR_CNP_FSM_CON,           0xB2 },
+	{ WCD937X_EAR_TEST_CTL,                  0x00 },
+	{ WCD937X_EAR_STATUS_REG_1,              0x00 },
+	{ WCD937X_EAR_STATUS_REG_2,              0x00 },
+	{ WCD937X_ANA_NEW_PAGE_REGISTER,         0x00 },
+	{ WCD937X_HPH_NEW_ANA_HPH2,              0x00 },
+	{ WCD937X_HPH_NEW_ANA_HPH3,              0x00 },
+	{ WCD937X_SLEEP_CTL,                     0x16 },
+	{ WCD937X_SLEEP_WATCHDOG_CTL,            0x00 },
+	{ WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL,  0x00 },
+	{ WCD937X_MBHC_NEW_CTL_1,                0x02 },
+	{ WCD937X_MBHC_NEW_CTL_2,                0x05 },
+	{ WCD937X_MBHC_NEW_PLUG_DETECT_CTL,      0xE9 },
+	{ WCD937X_MBHC_NEW_ZDET_ANA_CTL,         0x0F },
+	{ WCD937X_MBHC_NEW_ZDET_RAMP_CTL,        0x00 },
+	{ WCD937X_MBHC_NEW_FSM_STATUS,           0x00 },
+	{ WCD937X_MBHC_NEW_ADC_RESULT,           0x00 },
+	{ WCD937X_TX_NEW_TX_CH2_SEL,             0x00 },
+	{ WCD937X_AUX_AUXPA,                     0x00 },
+	{ WCD937X_LDORXTX_MODE,                  0x0C },
+	{ WCD937X_LDORXTX_CONFIG,                0x10 },
+	{ WCD937X_DIE_CRACK_DIE_CRK_DET_EN,      0x00 },
+	{ WCD937X_DIE_CRACK_DIE_CRK_DET_OUT,     0x00 },
+	{ WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL,     0x40 },
+	{ WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,    0x81 },
+	{ WCD937X_HPH_NEW_INT_RDAC_VREF_CTL,     0x10 },
+	{ WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00 },
+	{ WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,    0x81 },
+	{ WCD937X_HPH_NEW_INT_PA_MISC1,          0x22 },
+	{ WCD937X_HPH_NEW_INT_PA_MISC2,          0x00 },
+	{ WCD937X_HPH_NEW_INT_PA_RDAC_MISC,      0x00 },
+	{ WCD937X_HPH_NEW_INT_HPH_TIMER1,        0xFE },
+	{ WCD937X_HPH_NEW_INT_HPH_TIMER2,        0x02 },
+	{ WCD937X_HPH_NEW_INT_HPH_TIMER3,        0x4E },
+	{ WCD937X_HPH_NEW_INT_HPH_TIMER4,        0x54 },
+	{ WCD937X_HPH_NEW_INT_PA_RDAC_MISC2,     0x00 },
+	{ WCD937X_HPH_NEW_INT_PA_RDAC_MISC3,     0x00 },
+	{ WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62 },
+	{ WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP,  0x01 },
+	{ WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP,    0x11 },
+	{ WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57 },
+	{ WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01 },
+	{ WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT,  0x00 },
+	{ WCD937X_MBHC_NEW_INT_SPARE_2,           0x00 },
+	{ WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON,    0xA8 },
+	{ WCD937X_EAR_INT_NEW_CNP_VCM_CON1,       0x42 },
+	{ WCD937X_EAR_INT_NEW_CNP_VCM_CON2,       0x22 },
+	{ WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS,   0x00 },
+	{ WCD937X_AUX_INT_EN_REG,                 0x00 },
+	{ WCD937X_AUX_INT_PA_CTRL,                0x06 },
+	{ WCD937X_AUX_INT_SP_CTRL,                0xD2 },
+	{ WCD937X_AUX_INT_DAC_CTRL,               0x80 },
+	{ WCD937X_AUX_INT_CLK_CTRL,               0x50 },
+	{ WCD937X_AUX_INT_TEST_CTRL,              0x00 },
+	{ WCD937X_AUX_INT_STATUS_REG,             0x00 },
+	{ WCD937X_AUX_INT_MISC,                   0x00 },
+	{ WCD937X_LDORXTX_INT_BIAS,               0x6E },
+	{ WCD937X_LDORXTX_INT_STB_LOADS_DTEST,    0x50 },
+	{ WCD937X_LDORXTX_INT_TEST0,              0x1C },
+	{ WCD937X_LDORXTX_INT_STARTUP_TIMER,      0xFF },
+	{ WCD937X_LDORXTX_INT_TEST1,              0x1F },
+	{ WCD937X_LDORXTX_INT_STATUS,             0x00 },
+	{ WCD937X_SLEEP_INT_WATCHDOG_CTL_1,       0x0A },
+	{ WCD937X_SLEEP_INT_WATCHDOG_CTL_2,       0x0A },
+	{ WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02 },
+	{ WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60 },
+	{ WCD937X_DIGITAL_PAGE_REGISTER,          0x00 },
+	{ WCD937X_DIGITAL_CHIP_ID0,               0x00 },
+	{ WCD937X_DIGITAL_CHIP_ID1,               0x00 },
+	{ WCD937X_DIGITAL_CHIP_ID2,               0x0A },
+	{ WCD937X_DIGITAL_CHIP_ID3,               0x01 },
+	{ WCD937X_DIGITAL_CDC_RST_CTL,            0x03 },
+	{ WCD937X_DIGITAL_TOP_CLK_CFG,            0x00 },
+	{ WCD937X_DIGITAL_CDC_ANA_CLK_CTL,        0x00 },
+	{ WCD937X_DIGITAL_CDC_DIG_CLK_CTL,        0x00 },
+	{ WCD937X_DIGITAL_SWR_RST_EN,             0x00 },
+	{ WCD937X_DIGITAL_CDC_PATH_MODE,          0x55 },
+	{ WCD937X_DIGITAL_CDC_RX_RST,             0x00 },
+	{ WCD937X_DIGITAL_CDC_RX0_CTL,            0xFC },
+	{ WCD937X_DIGITAL_CDC_RX1_CTL,            0xFC },
+	{ WCD937X_DIGITAL_CDC_RX2_CTL,            0xFC },
+	{ WCD937X_DIGITAL_DEM_BYPASS_DATA0,       0x55 },
+	{ WCD937X_DIGITAL_DEM_BYPASS_DATA1,       0x55 },
+	{ WCD937X_DIGITAL_DEM_BYPASS_DATA2,       0x55 },
+	{ WCD937X_DIGITAL_DEM_BYPASS_DATA3,       0x01 },
+	{ WCD937X_DIGITAL_CDC_COMP_CTL_0,         0x00 },
+	{ WCD937X_DIGITAL_CDC_RX_DELAY_CTL,       0x66 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A1_0,       0x00 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A1_1,       0x01 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A2_0,       0x63 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A2_1,       0x04 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A3_0,       0xAC },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A3_1,       0x04 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A4_0,       0x1A },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A4_1,       0x03 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A5_0,       0xBC },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A5_1,       0x02 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A6_0,       0xC7 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_A7_0,       0xF8 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_C_0,        0x47 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_C_1,        0x43 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_C_2,        0xB1 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_C_3,        0x17 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R1,         0x4B },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R2,         0x27 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R3,         0x32 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R4,         0x57 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R4,         0x63 },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R4,         0x7C },
+	{ WCD937X_DIGITAL_CDC_HPH_DSM_R4,         0x57 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A1_0,       0x00 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A1_1,       0x01 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A2_0,       0x96 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A2_1,       0x09 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A3_0,       0xAB },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A3_1,       0x05 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A4_0,       0x1C },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A4_1,       0x02 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A5_0,       0x17 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A5_1,       0x02 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A6_0,       0xAA },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_A7_0,       0xE3 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_C_0,        0x69 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_C_1,        0x54 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_C_2,        0x02 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_C_3,        0x15 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R1,         0xA4 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R2,         0xB5 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R3,         0x86 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R4,         0x85 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R5,         0xAA },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R6,         0xE2 },
+	{ WCD937X_DIGITAL_CDC_AUX_DSM_R7,         0x62 },
+	{ WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0,      0x55 },
+	{ WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1,      0xA9 },
+	{ WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0,     0x3D },
+	{ WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1,     0x2E },
+	{ WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2,     0x01 },
+	{ WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0,     0x00 },
+	{ WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1,     0xFC },
+	{ WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2,     0x01 },
+	{ WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,       0x00 },
+	{ WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,       0x00 },
+	{ WCD937X_DIGITAL_CDC_EAR_PATH_CTL,       0x00 },
+	{ WCD937X_DIGITAL_CDC_SWR_CLH,            0x00 },
+	{ WCD937X_DIGITAL_SWR_CLH_BYP,            0x00 },
+	{ WCD937X_DIGITAL_CDC_TX0_CTL,            0x68 },
+	{ WCD937X_DIGITAL_CDC_TX1_CTL,            0x68 },
+	{ WCD937X_DIGITAL_CDC_TX2_CTL,            0x68 },
+	{ WCD937X_DIGITAL_CDC_TX_RST,             0x00 },
+	{ WCD937X_DIGITAL_CDC_REQ_CTL,            0x01 },
+	{ WCD937X_DIGITAL_CDC_AMIC_CTL,           0x07 },
+	{ WCD937X_DIGITAL_CDC_DMIC_CTL,           0x00 },
+	{ WCD937X_DIGITAL_CDC_DMIC0_CTL,          0x01 },
+	{ WCD937X_DIGITAL_CDC_DMIC1_CTL,          0x01 },
+	{ WCD937X_DIGITAL_CDC_DMIC2_CTL,          0x01 },
+	{ WCD937X_DIGITAL_EFUSE_CTL,              0x2B },
+	{ WCD937X_DIGITAL_EFUSE_PRG_CTL,          0x00 },
+	{ WCD937X_DIGITAL_EFUSE_TEST_CTL_0,       0x00 },
+	{ WCD937X_DIGITAL_EFUSE_TEST_CTL_1,       0x00 },
+	{ WCD937X_DIGITAL_EFUSE_T_DATA_0,         0x00 },
+	{ WCD937X_DIGITAL_EFUSE_T_DATA_1,         0x00 },
+	{ WCD937X_DIGITAL_PDM_WD_CTL0,            0x00 },
+	{ WCD937X_DIGITAL_PDM_WD_CTL1,            0x00 },
+	{ WCD937X_DIGITAL_PDM_WD_CTL2,            0x00 },
+	{ WCD937X_DIGITAL_INTR_MODE,              0x00 },
+	{ WCD937X_DIGITAL_INTR_MASK_0,            0xFF },
+	{ WCD937X_DIGITAL_INTR_MASK_1,            0xFF },
+	{ WCD937X_DIGITAL_INTR_MASK_2,            0xFF },
+	{ WCD937X_DIGITAL_INTR_STATUS_0,          0x00 },
+	{ WCD937X_DIGITAL_INTR_STATUS_1,          0x00 },
+	{ WCD937X_DIGITAL_INTR_STATUS_2,          0x00 },
+	{ WCD937X_DIGITAL_INTR_CLEAR_0,           0x00 },
+	{ WCD937X_DIGITAL_INTR_CLEAR_1,           0x00 },
+	{ WCD937X_DIGITAL_INTR_CLEAR_2,           0x00 },
+	{ WCD937X_DIGITAL_INTR_LEVEL_0,           0x00 },
+	{ WCD937X_DIGITAL_INTR_LEVEL_1,           0x00 },
+	{ WCD937X_DIGITAL_INTR_LEVEL_2,           0x00 },
+	{ WCD937X_DIGITAL_INTR_SET_0,             0x00 },
+	{ WCD937X_DIGITAL_INTR_SET_1,             0x00 },
+	{ WCD937X_DIGITAL_INTR_SET_2,             0x00 },
+	{ WCD937X_DIGITAL_INTR_TEST_0,            0x00 },
+	{ WCD937X_DIGITAL_INTR_TEST_1,            0x00 },
+	{ WCD937X_DIGITAL_INTR_TEST_2,            0x00 },
+	{ WCD937X_DIGITAL_CDC_CONN_RX0_CTL,       0x00 },
+	{ WCD937X_DIGITAL_CDC_CONN_RX1_CTL,       0x00 },
+	{ WCD937X_DIGITAL_CDC_CONN_RX2_CTL,       0x00 },
+	{ WCD937X_DIGITAL_CDC_CONN_TX_CTL,        0x00 },
+	{ WCD937X_DIGITAL_LOOP_BACK_MODE,         0x00 },
+	{ WCD937X_DIGITAL_SWR_DAC_TEST,           0x00 },
+	{ WCD937X_DIGITAL_SWR_HM_TEST_RX_0,       0x40 },
+	{ WCD937X_DIGITAL_SWR_HM_TEST_TX_0,       0x40 },
+	{ WCD937X_DIGITAL_SWR_HM_TEST_RX_1,       0x00 },
+	{ WCD937X_DIGITAL_SWR_HM_TEST_TX_1,       0x00 },
+	{ WCD937X_DIGITAL_SWR_HM_TEST,            0x00 },
+	{ WCD937X_DIGITAL_PAD_CTL_PDM_RX0,        0xF1 },
+	{ WCD937X_DIGITAL_PAD_CTL_PDM_RX1,        0xF1 },
+	{ WCD937X_DIGITAL_PAD_CTL_PDM_RX2,        0xF1 },
+	{ WCD937X_DIGITAL_PAD_CTL_PDM_TX,         0xF1 },
+	{ WCD937X_DIGITAL_PAD_INP_DIS_1,          0x00 },
+	{ WCD937X_DIGITAL_DRIVE_STRENGTH_0,       0x00 },
+	{ WCD937X_DIGITAL_DRIVE_STRENGTH_1,       0x00 },
+	{ WCD937X_DIGITAL_DRIVE_STRENGTH_2,       0x00 },
+	{ WCD937X_DIGITAL_RX_DATA_EDGE_CTL,       0x1F },
+	{ WCD937X_DIGITAL_TX_DATA_EDGE_CTL,       0x10 },
+	{ WCD937X_DIGITAL_GPIO_MODE,              0x00 },
+	{ WCD937X_DIGITAL_PIN_CTL_OE,             0x00 },
+	{ WCD937X_DIGITAL_PIN_CTL_DATA_0,         0x00 },
+	{ WCD937X_DIGITAL_PIN_CTL_DATA_1,         0x00 },
+	{ WCD937X_DIGITAL_PIN_STATUS_0,           0x00 },
+	{ WCD937X_DIGITAL_PIN_STATUS_1,           0x00 },
+	{ WCD937X_DIGITAL_DIG_DEBUG_CTL,          0x00 },
+	{ WCD937X_DIGITAL_DIG_DEBUG_EN,           0x00 },
+	{ WCD937X_DIGITAL_ANA_CSR_DBG_ADD,        0x00 },
+	{ WCD937X_DIGITAL_ANA_CSR_DBG_CTL,        0x48 },
+	{ WCD937X_DIGITAL_SSP_DBG,                0x00 },
+	{ WCD937X_DIGITAL_MODE_STATUS_0,          0x00 },
+	{ WCD937X_DIGITAL_MODE_STATUS_1,          0x00 },
+	{ WCD937X_DIGITAL_SPARE_0,                0x00 },
+	{ WCD937X_DIGITAL_SPARE_1,                0x00 },
+	{ WCD937X_DIGITAL_SPARE_2,                0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_0,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_1,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_2,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_3,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_4,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_5,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_6,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_7,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_8,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_9,            0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_10,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_11,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_12,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_13,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_14,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_15,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_16,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_17,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_18,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_19,           0xFF },
+	{ WCD937X_DIGITAL_EFUSE_REG_20,           0x0E },
+	{ WCD937X_DIGITAL_EFUSE_REG_21,           0x8F },
+	{ WCD937X_DIGITAL_EFUSE_REG_22,           0x16 },
+	{ WCD937X_DIGITAL_EFUSE_REG_23,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_24,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_25,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_26,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_27,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_28,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_29,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_30,           0x00 },
+	{ WCD937X_DIGITAL_EFUSE_REG_31,           0x00 },
+};
+
+static bool wcd937x_readable_register(struct device *dev, unsigned int reg)
+{
+	return wcd937x_reg_access[WCD937X_REG(reg)] & RD_REG;
+}
+
+static bool wcd937x_writeable_register(struct device *dev, unsigned int reg)
+{
+	return wcd937x_reg_access[WCD937X_REG(reg)] & WR_REG;
+}
+
+static bool wcd937x_volatile_register(struct device *dev, unsigned int reg)
+{
+	return (wcd937x_reg_access[WCD937X_REG(reg)] & RD_REG)
+		& ~(wcd937x_reg_access[WCD937X_REG(reg)] & WR_REG);
+}
+
+struct regmap_config wcd937x_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 8,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_defaults = wcd937x_defaults,
+	.num_reg_defaults = ARRAY_SIZE(wcd937x_defaults),
+	.max_register = WCD937X_MAX_REGISTER,
+	.readable_reg = wcd937x_readable_register,
+	.writeable_reg = wcd937x_writeable_register,
+	.volatile_reg = wcd937x_volatile_register,
+	.can_multi_write = true,
+};

+ 432 - 0
asoc/codecs/wcd937x/wcd937x-tables.c

@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2018 , The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include "wcd937x-registers.h"
+
+const u8 wcd937x_reg_access[WCD937X_REG(WCD937X_REGISTERS_MAX_SIZE)] = {
+	[WCD937X_REG(WCD937X_ANA_BIAS)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_RX_SUPPLIES)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_HPH)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_EAR)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_EAR_COMPANDER_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_TX_CH1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_TX_CH2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_TX_CH3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_TX_CH3_HPF)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MICB3_DSP_EN_LOGIC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_MECH)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_ELECT)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_ZDET)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_RESULT_1)] = RD_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_RESULT_2)] = RD_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_RESULT_3)] = RD_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN5)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN6)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MBHC_BTN7)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MICB1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MICB2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MICB2_RAMP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_ANA_MICB3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_BIAS_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_BIAS_VBG_FINE_ADJ)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDOL_VDDCX_ADJUST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDOL_DISABLE_LDOL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_CTL_CLK)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_CTL_ANA)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_CTL_SPARE_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_CTL_SPARE_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_CTL_BCS)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_MOISTURE_DET_FSM_STATUS)] = RD_REG,
+	[WCD937X_REG(WCD937X_MBHC_TEST_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDOH_MODE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDOH_BIAS)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDOH_STB_LOADS)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDOH_SLOWRAMP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB1_TEST_CTL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB1_TEST_CTL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB1_TEST_CTL_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB2_TEST_CTL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB2_TEST_CTL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB2_TEST_CTL_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB3_TEST_CTL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB3_TEST_CTL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MICB3_TEST_CTL_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_ADC_VCM)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_BIAS_ATEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_ADC_INT1_IB)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_ADC_INT2_IB)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_START)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_STOP_9P6M)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_STOP_12P288M)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_TEST_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_ADC_IB)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_ATEST_REFCTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_TEST_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_TEST_BLK_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_TXFE_CLKDIV)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_SAR2_ERR)] = RD_REG,
+	[WCD937X_REG(WCD937X_TX_1_2_SAR1_ERR)] = RD_REG,
+	[WCD937X_REG(WCD937X_TX_3_TEST_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_3_ADC_IB)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_3_ATEST_REFCTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_3_TEST_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_3_TEST_BLK_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_3_TXFE_CLKDIV)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_TX_3_SPARE_MONO)] = RD_REG,
+	[WCD937X_REG(WCD937X_TX_3_SAR1_ERR)] = RD_REG,
+	[WCD937X_REG(WCD937X_CLASSH_MODE_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_MODE_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_MODE_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_VCL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_VCL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_5)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_BUCK_TMUX_A_D)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_BUCK_SW_DRV_CNTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_CLASSH_SPARE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_5)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_6)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_7)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_8)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_9)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEGDAC_CTRL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEGDAC_CTRL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_VNEGDAC_CTRL_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_CTRL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_FLYBACK_TEST_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_AUX_SW_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_PA_AUX_IN_CONN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_TIMER_DIV)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_OCP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_OCP_COUNT)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_EAR_DAC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_EAR_AMP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_HPH_LDO)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_HPH_PA)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_HPH_RDAC_LDO)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_HPH_CNP1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_HPH_LOWPOWER)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_AUX_DAC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_AUX_AMP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_VNEGDAC_BLEEDER)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_MISC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_BUCK_RST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_BUCK_VREF_ERRAMP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_FLYB_ERRAMP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_FLYB_BUFF)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_BIAS_FLYB_MID_RST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_L_STATUS)] = RD_REG,
+	[WCD937X_REG(WCD937X_HPH_R_STATUS)] = RD_REG,
+	[WCD937X_REG(WCD937X_HPH_CNP_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_CNP_WG_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_CNP_WG_TIME)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_OCP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_AUTO_CHOP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_CHOP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_PA_CTL1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_PA_CTL2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_L_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_L_TEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_L_ATEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_R_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_R_TEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_R_ATEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_RDAC_CLK_CTL1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_RDAC_CLK_CTL2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_RDAC_LDO_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_REFBUFF_UHQA_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_REFBUFF_LP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_L_DAC_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_R_DAC_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS)] = RD_REG,
+	[WCD937X_REG(WCD937X_EAR_EAR_EN_REG)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_EAR_PA_CON)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_EAR_SP_CON)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_EAR_DAC_CON)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_EAR_CNP_FSM_CON)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_TEST_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_STATUS_REG_1)] = RD_REG,
+	[WCD937X_REG(WCD937X_EAR_STATUS_REG_2)] = RD_REG,
+	[WCD937X_REG(WCD937X_ANA_NEW_PAGE_REGISTER)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_ANA_HPH2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_ANA_HPH3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_SLEEP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_SLEEP_WATCHDOG_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_CTL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_CTL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_PLUG_DETECT_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_ZDET_ANA_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_ZDET_RAMP_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_FSM_STATUS)] = RD_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_ADC_RESULT)] = RD_REG,
+	[WCD937X_REG(WCD937X_TX_NEW_TX_CH2_SEL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_AUXPA)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_MODE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_CONFIG)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIE_CRACK_DIE_CRK_DET_EN)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIE_CRACK_DIE_CRK_DET_OUT)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_VREF_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_MISC1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_MISC2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_RDAC_MISC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_RDAC_MISC2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_RDAC_MISC3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL)]
+								= RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_MBHC_NEW_INT_SPARE_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_INT_NEW_CNP_VCM_CON1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_INT_NEW_CNP_VCM_CON2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_EN_REG)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_PA_CTRL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_SP_CTRL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_DAC_CTRL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_CLK_CTRL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_TEST_CTRL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_STATUS_REG)] = RD_REG,
+	[WCD937X_REG(WCD937X_AUX_INT_MISC)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_INT_BIAS)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_INT_STB_LOADS_DTEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_INT_TEST0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_INT_STARTUP_TIMER)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_INT_TEST1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_LDORXTX_INT_STATUS)] = RD_REG,
+	[WCD937X_REG(WCD937X_SLEEP_INT_WATCHDOG_CTL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_SLEEP_INT_WATCHDOG_CTL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAGE_REGISTER)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID0)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID1)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID2)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID3)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_RST_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_TOP_CLK_CFG)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_ANA_CLK_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_DIG_CLK_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_RST_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_PATH_MODE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_RX_RST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_RX0_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_RX1_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_RX2_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_COMP_CTL_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_RX_DELAY_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A1_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A1_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A2_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A2_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A3_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A3_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A4_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A4_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A5_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A5_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A6_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A7_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A1_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A1_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A2_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A2_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A3_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A3_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A4_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A4_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A5_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A5_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A6_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A7_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R5)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R6)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R7)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_EAR_PATH_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_SWR_CLH)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_CLH_BYP)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_TX0_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_TX1_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_TX2_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_TX_RST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_REQ_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_AMIC_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC0_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC1_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC2_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_PRG_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_TEST_CTL_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_TEST_CTL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_T_DATA_0)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_T_DATA_1)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PDM_WD_CTL0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PDM_WD_CTL1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PDM_WD_CTL2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_MODE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_MASK_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_MASK_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_MASK_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_STATUS_0)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_STATUS_1)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_STATUS_2)] = RD_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_CLEAR_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_CLEAR_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_CLEAR_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_LEVEL_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_LEVEL_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_LEVEL_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_SET_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_SET_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_SET_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_TEST_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_TEST_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_INTR_TEST_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_RX0_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_RX1_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_RX2_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_TX_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_LOOP_BACK_MODE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_DAC_TEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_RX_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_TX_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_RX_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_TX_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_RX0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_RX1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_RX2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_TX)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_TX)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PAD_INP_DIS_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DRIVE_STRENGTH_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DRIVE_STRENGTH_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DRIVE_STRENGTH_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_RX_DATA_EDGE_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_TX_DATA_EDGE_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_GPIO_MODE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PIN_CTL_OE)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PIN_CTL_DATA_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PIN_CTL_DATA_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PIN_STATUS_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_PIN_STATUS_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DIG_DEBUG_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_DIG_DEBUG_EN)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_ANA_CSR_DBG_ADD)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_ANA_CSR_DBG_CTL)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SSP_DBG)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_MODE_STATUS_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_MODE_STATUS_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SPARE_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SPARE_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_SPARE_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_0)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_1)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_2)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_3)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_4)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_5)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_6)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_7)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_8)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_9)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_10)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_11)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_12)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_13)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_14)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_15)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_16)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_17)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_18)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_19)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_20)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_21)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_22)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_23)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_24)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_25)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_26)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_27)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_28)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_29)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_30)] = RD_WR_REG,
+	[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_31)] = RD_WR_REG,
+};

+ 1412 - 0
asoc/codecs/wcd937x/wcd937x.c

@@ -0,0 +1,1412 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/component.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include <soc/soundwire.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include "internal.h"
+#include "../wcdcal-hwdep.h"
+#include "wcd937x-registers.h"
+#include "../msm-cdc-pinctrl.h"
+
+#define WCD9370_VARIANT 0
+#define WCD9375_VARIANT 5
+
+static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
+
+static int wcd937x_init_reg(struct snd_soc_codec *codec)
+{
+	snd_soc_update_bits(codec, WCD937X_SLEEP_CTL, 0x0E, 0x0E);
+	snd_soc_update_bits(codec, WCD937X_SLEEP_CTL, 0x80, 0x80);
+	usleep_range(1000, 1010);
+	snd_soc_update_bits(codec, WCD937X_SLEEP_CTL, 0x40, 0x40);
+	usleep_range(1000, 1010);
+	snd_soc_update_bits(codec, WCD937X_LDORXTX_CONFIG, 0x10, 0x00);
+	snd_soc_update_bits(codec, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0x80);
+	snd_soc_update_bits(codec, WCD937X_ANA_BIAS, 0x80, 0x80);
+	snd_soc_update_bits(codec, WCD937X_ANA_BIAS, 0x40, 0x40);
+	usleep_range(10000, 10010);
+	snd_soc_update_bits(codec, WCD937X_ANA_BIAS, 0x40, 0x00);
+
+	return 0;
+}
+
+static int wcd937x_rx_clk_enable(struct snd_soc_codec *codec)
+{
+
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+
+	if (wcd937x->rx_clk_cnt == 0) {
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x08, 0x08);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x01, 0x01);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_RX0_CTL,
+				    0x40, 0x00);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x02, 0x02);
+	}
+	wcd937x->rx_clk_cnt++;
+
+	return 0;
+}
+
+static int wcd937x_rx_clk_disable(struct snd_soc_codec *codec)
+{
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+
+	wcd937x->rx_clk_cnt--;
+	if (wcd937x->rx_clk_cnt == 0) {
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES, 0x40, 0x00);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES, 0x80, 0x00);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x02, 0x00);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x01, 0x00);
+	}
+	return 0;
+}
+
+static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd937x_rx_clk_enable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x01, 0x01);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
+				    0x04, 0x04);
+		snd_soc_update_bits(codec, WCD937X_HPH_RDAC_CLK_CTL1,
+				    0x80, 0x00);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		snd_soc_update_bits(codec, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
+				    0x0F, 0x02);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_COMP_CTL_0,
+				    0x02, 0x02);
+		usleep_range(5000, 5010);
+		snd_soc_update_bits(codec, WCD937X_HPH_NEW_INT_HPH_TIMER1,
+				    0x02, 0x00);
+		break;
+	}
+
+	return 0;
+}
+
+static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd937x_rx_clk_enable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
+				    0x08, 0x08);
+		snd_soc_update_bits(codec, WCD937X_HPH_RDAC_CLK_CTL1,
+				    0x80, 0x00);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		snd_soc_update_bits(codec, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
+				    0x0F, 0x02);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_COMP_CTL_0,
+				    0x01, 0x01);
+		usleep_range(5000, 5010);
+		snd_soc_update_bits(codec, WCD937X_HPH_NEW_INT_HPH_TIMER1,
+				    0x02, 0x00);
+		break;
+	}
+
+	return 0;
+}
+
+static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd937x_rx_clk_enable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
+				    0x04, 0x04);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x01, 0x01);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_COMP_CTL_0,
+				    0x02, 0x02);
+		usleep_range(5000, 5010);
+		break;
+	};
+	return 0;
+
+}
+
+static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd937x_rx_clk_enable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x04, 0x04);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x04, 0x04);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
+				    0x01, 0x01);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd937x_rx_clk_disable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x04, 0x00);
+		break;
+	};
+	return 0;
+
+}
+
+static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_ANA_HPH, 0x10, 0x10);
+		usleep_range(100, 110);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		usleep_range(7000, 7010);
+		snd_soc_update_bits(codec, WCD937X_HPH_NEW_INT_HPH_TIMER1,
+				    0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x02, 0x02);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		usleep_range(7000, 7010);
+		snd_soc_update_bits(codec, WCD937X_ANA_HPH, 0x10, 0x00);
+		break;
+	};
+	return 0;
+}
+
+static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_ANA_HPH, 0x0C, 0x08);
+		snd_soc_update_bits(codec, WCD937X_ANA_HPH, 0x20, 0x20);
+		usleep_range(100, 110);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		usleep_range(7000, 7010);
+		snd_soc_update_bits(codec, WCD937X_HPH_NEW_INT_HPH_TIMER1,
+				    0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x02, 0x02);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		usleep_range(7000, 7010);
+		snd_soc_update_bits(codec, WCD937X_ANA_HPH, 0x20, 0x00);
+		break;
+	};
+	return 0;
+}
+
+static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x80, 0x80);
+		usleep_range(500, 510);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2, 0xFF, 0x3A);
+		usleep_range(500, 510);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		usleep_range(1000, 1010);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x20, 0x20);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		usleep_range(1000, 1010);
+		usleep_range(1000, 1010);
+		break;
+	};
+	return 0;
+}
+
+static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x08, 0x08);
+		usleep_range(500, 510);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2, 0xFF, 0x3A);
+		usleep_range(500, 510);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		usleep_range(6000, 6010);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x02, 0x02);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		usleep_range(7000, 7010);
+		break;
+	};
+	return 0;
+}
+
+static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol,
+			      int event)
+{
+
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEG_CTRL_4,
+				    0xF0, 0x80);
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEGDAC_CTRL_2,
+				    0xE0, 0xA0);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_3,
+				    0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2,
+				    0xFF, 0x1C);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x40, 0x40);
+		usleep_range(100, 110);
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEGDAC_CTRL_2,
+				    0xE0, 0xE0);
+		usleep_range(100, 110);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x80, 0x80);
+		usleep_range(500, 510);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2, 0xFF, 0x3A);
+		usleep_range(500, 510);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd937x_rx_clk_disable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x01, 0x00);
+		break;
+	};
+	return 0;
+}
+static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEG_CTRL_4,
+				    0xF0, 0x80);
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEGDAC_CTRL_2,
+				    0xE0, 0xA0);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_3, 0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2, 0xFF, 0x1C);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x40, 0x40);
+		usleep_range(100, 110);
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEGDAC_CTRL_2,
+				    0xE0, 0xE0);
+		usleep_range(100, 110);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x80, 0x80);
+		usleep_range(500, 510);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2, 0xFF, 0x3A);
+		usleep_range(500, 510);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd937x_rx_clk_disable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x02, 0x00);
+		break;
+	};
+
+	return 0;
+}
+
+static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol,
+			      int event)
+{
+
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEG_CTRL_2,
+				    0xE0, 0xA0);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_3, 0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_CLASSH_MODE_2, 0xFF, 0x1C);
+		snd_soc_update_bits(codec, WCD937X_ANA_RX_SUPPLIES,
+				    0x40, 0x40);
+		usleep_range(100, 110);
+		snd_soc_update_bits(codec, WCD937X_FLYBACK_VNEG_CTRL_2,
+				    0xE0, 0xE0);
+		usleep_range(100, 110);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		usleep_range(6000, 6010);
+		wcd937x_rx_clk_disable(codec);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x04, 0x00);
+		break;
+	}
+	return 0;
+
+}
+
+static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
+				     struct snd_kcontrol *kcontrol,
+				     int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+	u16 dmic_clk_reg;
+	s32 *dmic_clk_cnt;
+	unsigned int dmic;
+	char *wname;
+	int ret = 0;
+
+	wname = strpbrk(w->name, "012345");
+
+	if (!wname) {
+		dev_err(codec->dev, "%s: widget not found\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = kstrtouint(wname, 10, &dmic);
+	if (ret < 0) {
+		dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (dmic) {
+	case 0:
+	case 1:
+		dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
+		dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC0_CTL;
+		break;
+	case 2:
+	case 3:
+		dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
+		dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
+		break;
+	case 4:
+	case 5:
+		dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
+		dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
+		break;
+	default:
+		dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
+			__func__);
+		return -EINVAL;
+	};
+	dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
+			__func__, event,  dmic, *dmic_clk_cnt);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x80, 0x80);
+		snd_soc_update_bits(codec, dmic_clk_reg, 0x07, 0x02);
+		snd_soc_update_bits(codec, dmic_clk_reg, 0x08, 0x08);
+		snd_soc_update_bits(codec, dmic_clk_reg, 0x70, 0x20);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		break;
+
+	};
+	return 0;
+}
+
+static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
+				    struct snd_kcontrol *kcontrol,
+				    int event){
+
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x80, 0x80);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x08, 0x08);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x10, 0x10);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x08, 0x00);
+		break;
+	};
+
+	return 0;
+}
+
+static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+	dev_dbg(codec->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_REQ_CTL,
+				    0x02, 0x02);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_REQ_CTL, 0x01,
+				    0x00);
+		snd_soc_update_bits(codec, WCD937X_ANA_TX_CH2, 0x40, 0x40);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x10, 0x10);
+		snd_soc_update_bits(codec, WCD937X_ANA_TX_CH1, 0x80, 0x80);
+		snd_soc_update_bits(codec, WCD937X_ANA_TX_CH2, 0x40, 0x00);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		snd_soc_update_bits(codec, WCD937X_ANA_TX_CH1, 0x80, 0x00);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x10, 0x00);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
+				    0x10, 0x00);
+		snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
+				    0x80, 0x00);
+		break;
+	};
+	return 0;
+}
+
+static int wcd937x_micbias_control(struct snd_soc_codec *codec,
+				   int micb_num, int req, bool is_dapm)
+{
+
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+	int micb_index = micb_num - 1;
+	u16 micb_reg;
+	int pre_off_event = 0, post_off_event = 0;
+	int post_on_event = 0, post_dapm_off = 0;
+	int post_dapm_on = 0;
+
+	if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
+		dev_err(codec->dev, "%s: Invalid micbias index, micb_ind:%d\n",
+			__func__, micb_index);
+		return -EINVAL;
+	}
+	switch (micb_num) {
+	case MIC_BIAS_1:
+		micb_reg = WCD937X_ANA_MICB1;
+		break;
+	case MIC_BIAS_2:
+		micb_reg = WCD937X_ANA_MICB2;
+		pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
+		post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
+		post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
+		post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
+		post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
+		break;
+	case MIC_BIAS_3:
+		micb_reg = WCD937X_ANA_MICB3;
+		break;
+	default:
+		dev_err(codec->dev, "%s: Invalid micbias number: %d\n",
+			__func__, micb_num);
+		return -EINVAL;
+	};
+	mutex_lock(&wcd937x->micb_lock);
+
+	switch (req) {
+	case MICB_PULLUP_ENABLE:
+		wcd937x->pullup_ref[micb_index]++;
+		if ((wcd937x->pullup_ref[micb_index] == 1) &&
+		    (wcd937x->micb_ref[micb_index] == 0))
+			snd_soc_update_bits(codec, micb_reg, 0xC0, 0x80);
+		break;
+	case MICB_PULLUP_DISABLE:
+		if (wcd937x->pullup_ref[micb_index] > 0)
+			wcd937x->pullup_ref[micb_index]--;
+		if ((wcd937x->pullup_ref[micb_index] == 0) &&
+		    (wcd937x->micb_ref[micb_index] == 0))
+			snd_soc_update_bits(codec, micb_reg, 0xC0, 0x00);
+		break;
+	case MICB_ENABLE:
+		wcd937x->micb_ref[micb_index]++;
+		if (wcd937x->micb_ref[micb_index] == 1) {
+			snd_soc_update_bits(codec, micb_reg, 0xC0, 0x40);
+			if (post_on_event)
+				blocking_notifier_call_chain(&wcd937x->notifier,
+							     post_on_event,
+							     &wcd937x->mbhc);
+		}
+		if (is_dapm && post_dapm_on)
+			blocking_notifier_call_chain(&wcd937x->notifier,
+						     post_dapm_on,
+						     &wcd937x->mbhc);
+		break;
+	case MICB_DISABLE:
+		if (wcd937x->micb_ref[micb_index] > 0)
+			wcd937x->micb_ref[micb_index]--;
+		if ((wcd937x->micb_ref[micb_index] == 0) &&
+		    (wcd937x->pullup_ref[micb_index] > 0))
+			snd_soc_update_bits(codec, micb_reg, 0xC0, 0x80);
+		else if ((wcd937x->micb_ref[micb_index] == 0) &&
+			 (wcd937x->pullup_ref[micb_index] == 0)) {
+			if (pre_off_event)
+				blocking_notifier_call_chain(&wcd937x->notifier,
+							     pre_off_event,
+							     &wcd937x->mbhc);
+			snd_soc_update_bits(codec, micb_reg, 0xC0, 0x00);
+			if (post_off_event)
+				blocking_notifier_call_chain(&wcd937x->notifier,
+							     post_off_event,
+							     &wcd937x->mbhc);
+		}
+		if (is_dapm && post_dapm_off)
+			blocking_notifier_call_chain(&wcd937x->notifier,
+							post_dapm_off,
+							&wcd937x->mbhc);
+		break;
+	};
+
+	dev_dbg(codec->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
+		__func__, micb_num, wcd937x->micb_ref[micb_index],
+		wcd937x->pullup_ref[micb_index]);
+	mutex_unlock(&wcd937x->micb_lock);
+
+	return 0;
+}
+
+static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+					  int event)
+{
+	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+	int micb_num;
+
+	dev_dbg(codec->dev, "%s: wname: %s, event: %d\n",
+		__func__, w->name, event);
+
+	if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
+		micb_num = MIC_BIAS_1;
+	else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
+		micb_num = MIC_BIAS_2;
+	else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
+		micb_num = MIC_BIAS_3;
+	else
+		return -EINVAL;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd937x_micbias_control(codec, micb_num, MICB_ENABLE, true);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		usleep_range(1000, 1100);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd937x_micbias_control(codec, micb_num, MICB_DISABLE, true);
+		break;
+	};
+
+	return 0;
+
+}
+
+static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	return __wcd937x_codec_enable_micbias(w, event);
+}
+
+static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = wcd937x->hph_mode;
+	return 0;
+}
+
+static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+	u32 mode_val;
+
+	mode_val = ucontrol->value.enumerated.item[0];
+
+	dev_dbg(codec->dev, "%s: mode: %d\n", __func__, mode_val);
+
+	if (mode_val == 0) {
+		dev_warn(codec->dev, "%s:Invalid HPH Mode, default to class_AB\n",
+			__func__);
+		mode_val = 3; /* enum will be updated later */
+	}
+	wcd937x->hph_mode = mode_val;
+	return 0;
+}
+
+static const char * const rx_hph_mode_mux_text[] = {
+	"CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
+	"CLS_H_ULP", "CLS_AB_HIFI",
+};
+
+static const struct soc_enum rx_hph_mode_mux_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
+			    rx_hph_mode_mux_text);
+
+static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
+	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
+		wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
+
+	SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
+	SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
+	SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain),
+	SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain),
+	SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain),
+};
+
+static const struct snd_kcontrol_new adc1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new adc2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new adc3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic4_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic5_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic6_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new ear_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new aux_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphl_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphr_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const char * const adc2_mux_text[] = {
+	"INP2", "INP3"
+};
+
+static const char * const rdac3_mux_text[] = {
+	"RX1", "RX3"
+};
+
+static const struct soc_enum adc2_enum =
+	SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
+		ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
+
+
+static const struct soc_enum rdac3_enum =
+	SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
+		ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
+
+static const struct snd_kcontrol_new tx_adc2_mux =
+	SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
+
+static const struct snd_kcontrol_new rx_rdac3_mux =
+	SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
+
+static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
+
+	/*input widgets*/
+
+	SND_SOC_DAPM_INPUT("AMIC1"),
+	SND_SOC_DAPM_INPUT("AMIC2"),
+	SND_SOC_DAPM_INPUT("AMIC3"),
+	SND_SOC_DAPM_INPUT("IN1_HPHL"),
+	SND_SOC_DAPM_INPUT("IN2_HPHR"),
+	SND_SOC_DAPM_INPUT("IN3_AUX"),
+
+	/*tx widgets*/
+	SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
+				NULL, 0, wcd937x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
+				NULL, 0, wcd937x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc2_mux),
+
+	/*tx mixers*/
+	SND_SOC_DAPM_MIXER("ADC1_MIXER", SND_SOC_NOPM, 0,
+				0, adc1_switch, ARRAY_SIZE(adc1_switch)),
+	SND_SOC_DAPM_MIXER("ADC2_MIXER", SND_SOC_NOPM, 0,
+				0, adc2_switch, ARRAY_SIZE(adc2_switch)),
+
+	/* micbias widgets*/
+	SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+
+	/*rx widgets*/
+	SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
+				wcd937x_codec_enable_ear_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
+				wcd937x_codec_enable_aux_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
+				wcd937x_codec_enable_hphl_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
+				wcd937x_codec_enable_hphr_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_hphl_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_hphr_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_ear_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_aux_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
+
+	SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+
+	/* rx mixer widgets*/
+
+	SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
+			   ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
+	SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
+			   aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
+	SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
+			   hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
+	SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
+			   hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
+
+	/*output widgets tx*/
+
+	SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
+
+	/*output widgets rx*/
+	SND_SOC_DAPM_OUTPUT("EAR"),
+	SND_SOC_DAPM_OUTPUT("AUX"),
+	SND_SOC_DAPM_OUTPUT("HPHL"),
+	SND_SOC_DAPM_OUTPUT("HPHR"),
+
+};
+
+static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
+
+	/*input widgets*/
+	SND_SOC_DAPM_INPUT("AMIC4"),
+
+	/*tx widgets*/
+	SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
+				NULL, 0, wcd937x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 0, 0,
+				wcd937x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/*tx mixer widgets*/
+	SND_SOC_DAPM_MIXER("DMIC1_MIXER", SND_SOC_NOPM, 0,
+				0, dmic1_switch, ARRAY_SIZE(dmic1_switch)),
+	SND_SOC_DAPM_MIXER("DMIC2_MIXER", SND_SOC_NOPM, 0,
+				0, dmic2_switch, ARRAY_SIZE(dmic2_switch)),
+	SND_SOC_DAPM_MIXER("DMIC3_MIXER", SND_SOC_NOPM, 0,
+				0, dmic3_switch, ARRAY_SIZE(dmic3_switch)),
+	SND_SOC_DAPM_MIXER("DMIC4_MIXER", SND_SOC_NOPM, 0,
+				0, dmic4_switch, ARRAY_SIZE(dmic4_switch)),
+	SND_SOC_DAPM_MIXER("DMIC5_MIXER", SND_SOC_NOPM, 0,
+				0, dmic5_switch, ARRAY_SIZE(dmic5_switch)),
+	SND_SOC_DAPM_MIXER("DMIC6_MIXER", SND_SOC_NOPM, 0,
+				0, dmic6_switch, ARRAY_SIZE(dmic6_switch)),
+	SND_SOC_DAPM_MIXER("ADC3_MIXER", SND_SOC_NOPM, 0,
+				0, adc3_switch, ARRAY_SIZE(adc3_switch)),
+
+	/*output widgets*/
+	SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
+
+};
+
+static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
+
+	{"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
+	{"ADC2_MIXER", "Switch", "ADC2 REQ"},
+	{"ADC2 REQ", "NULL", "ADC2"},
+	{"ADC2", "NULL", "ADC2 MUX"},
+	{"ADC2 MUX", "INP3", "AMIC3"},
+	{"ADC2 MUX", "INP2", "AMIC2"},
+
+
+	{"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
+	{"ADC1_MIXER", "Switch", "ADC1 REQ"},
+	{"ADC1 REQ", NULL, "ADC1"},
+	{"ADC1", NULL, "AMIC1"},
+
+	{"RX1", NULL, "IN1_HPHL"},
+	{"RDAC1", NULL, "RX1"},
+	{"HPHL_RDAC", "Switch", "RDAC1"},
+	{"HPHL PGA", NULL, "HPHL_RDAC"},
+	{"HPHL", NULL, "HPHL PGA"},
+
+	{"RX2", NULL, "IN2_HPHR"},
+	{"RDAC2", NULL, "RX2"},
+	{"HPHR_RDAC", "Switch", "RDAC2"},
+	{"HPHR PGA", NULL, "HPHR_RDAC"},
+	{"HPHR", NULL, "HPHR PGA"},
+
+	{"RX3", NULL, "IN3_AUX"},
+	{"RDAC4", NULL, "RX3"},
+	{"AUX_RDAC", "Switch", "RDAC4"},
+	{"AUX PGA", NULL, "AUX_RDAC"},
+	{"AUX", NULL, "AUX PGA"},
+
+	{"RDAC3_MUX", "RX3", "RX3"},
+	{"RDAC3_MUX", "RX1", "RX1"},
+	{"RDAC3", NULL, "RDAC3_MUX"},
+	{"EAR_RDAC", "Switch", "RDAC3"},
+	{"EAR PGA", NULL, "EAR_RDAC"},
+	{"EAR", NULL, "EAR PGA"},
+
+};
+
+static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
+
+	{"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
+	{"ADC3_MIXER", "Switch", "ADC3 REQ"},
+	{"ADC3 REQ", NULL, "ADC3"},
+	{"ADC3", NULL, "AMIC4"},
+
+	{"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
+	{"DMIC1_MIXER", "Switch", "DMIC1"},
+
+	{"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
+	{"DMIC2_MIXER", "Switch", "DMIC2"},
+
+	{"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
+	{"DMIC3_MIXER", "Switch", "DMIC3"},
+
+	{"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
+	{"DMIC4_MIXER", "Switch", "DMIC4"},
+
+	{"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
+	{"DMIC5_MIXER", "Switch", "DMIC5"},
+
+	{"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
+	{"DMIC6_MIXER", "Switch", "DMIC6"},
+
+};
+
+static int wcd937x_soc_codec_probe(struct snd_soc_codec *codec)
+{
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
+	int variant;
+	int ret = -EINVAL;
+
+	dev_info(codec->dev, "%s()\n", __func__);
+	wcd937x = snd_soc_codec_get_drvdata(codec);
+
+	if (!wcd937x)
+		return -EINVAL;
+
+	wcd937x->codec = codec;
+
+	variant = (snd_soc_read(codec, WCD937X_DIGITAL_EFUSE_REG_0) & 0x0E) >> 1;
+	wcd937x->variant = variant;
+
+	wcd937x->fw_data = devm_kzalloc(codec->dev,
+					sizeof(*(wcd937x->fw_data)),
+					GFP_KERNEL);
+	if (!wcd937x->fw_data) {
+		dev_err(codec->dev, "Failed to allocate fw_data\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
+	ret = wcd_cal_create_hwdep(wcd937x->fw_data,
+				   WCD9XXX_CODEC_HWDEP_NODE, codec);
+
+	if (ret < 0) {
+		dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret);
+		goto err_hwdep;
+	}
+
+	wcd937x_init_reg(codec);
+
+	if (wcd937x->variant == WCD9375_VARIANT) {
+		ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
+					ARRAY_SIZE(wcd9375_dapm_widgets));
+		if (ret < 0) {
+			dev_err(codec->dev, "%s: Failed to add snd_ctls\n",
+				__func__);
+			goto err_hwdep;
+		}
+		ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
+					ARRAY_SIZE(wcd9375_audio_map));
+		if (ret < 0) {
+			dev_err(codec->dev, "%s: Failed to add routes\n",
+				__func__);
+			goto err_hwdep;
+		}
+		ret = snd_soc_dapm_new_widgets(dapm->card);
+		if (ret < 0) {
+			dev_err(codec->dev, "%s: Failed to add widgets\n",
+				__func__);
+			goto err_hwdep;
+		}
+	}
+	return ret;
+
+err_hwdep:
+	wcd937x->fw_data = NULL;
+
+err:
+	return ret;
+}
+
+static int wcd937x_soc_codec_remove(struct snd_soc_codec *codec)
+{
+	struct wcd937x_priv *wcd937x = snd_soc_codec_get_drvdata(codec);
+
+	if (!wcd937x)
+		return -EINVAL;
+
+	return 0;
+}
+
+static struct regmap *wcd937x_get_regmap(struct device *dev)
+{
+	struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
+
+	return wcd937x->regmap;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wcd937x = {
+	.probe = wcd937x_soc_codec_probe,
+	.remove = wcd937x_soc_codec_remove,
+	.get_regmap = wcd937x_get_regmap,
+	.component_driver = {
+		.controls = wcd937x_snd_controls,
+		.num_controls = ARRAY_SIZE(wcd937x_snd_controls),
+		.dapm_widgets = wcd937x_dapm_widgets,
+		.num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
+		.dapm_routes = wcd937x_audio_map,
+		.num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
+	},
+};
+
+int wcd937x_reset(struct device *dev)
+{
+	struct wcd937x_priv *wcd937x = NULL;
+	int rc = 0;
+	int value = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd937x = dev_get_drvdata(dev);
+	if (!wcd937x)
+		return -EINVAL;
+
+	if (!wcd937x->rst_np) {
+		dev_err(dev, "%s: reset gpio device node not specified\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
+	if (value > 0)
+		return 0;
+
+	rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
+	if (rc) {
+		dev_err(dev, "%s: wcd sleep state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20ms sleep required after pulling the reset gpio to LOW */
+	usleep_range(20, 30);
+
+	rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
+	if (rc) {
+		dev_err(dev, "%s: wcd active state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20ms sleep required after pulling the reset gpio to HIGH */
+	usleep_range(20, 30);
+
+	return rc;
+}
+
+struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
+{
+	struct wcd937x_pdata *pdata = NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(struct wcd937x_pdata),
+				GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	pdata->rst_np = of_parse_phandle(dev->of_node,
+			"qcom,wcd937x-reset-node", 0);
+
+	if (!pdata->rst_np) {
+		dev_err(dev, "%s: Looking up %s property in node %s failed\n",
+				__func__, "qcom,wcd937x-reset-node",
+				dev->of_node->full_name);
+		return NULL;
+	}
+
+	pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
+	pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
+
+	return pdata;
+}
+
+static int wcd937x_bind(struct device *dev)
+{
+	int ret = 0;
+	struct wcd937x_priv *wcd937x = NULL;
+	struct wcd937x_pdata *pdata = NULL;
+
+	wcd937x = devm_kzalloc(dev, sizeof(struct wcd937x_priv), GFP_KERNEL);
+	if (!wcd937x)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, wcd937x);
+
+	pdata = wcd937x_populate_dt_data(dev);
+	if (!pdata) {
+		dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd937x->rst_np = pdata->rst_np;
+	wcd937x_reset(dev);
+	/*
+	 * Add 5msec delay to provide sufficient time for
+	 * soundwire auto enumeration of slave devices as
+	 * as per HW requirement.
+	 */
+	usleep_range(5000, 5010);
+	ret = component_bind_all(dev, wcd937x);
+	if (ret) {
+		dev_err(dev, "%s: Slave bind failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
+	if (!wcd937x->rx_swr_dev) {
+		dev_err(dev, "%s: Could not find RX swr slave device\n",
+			 __func__);
+		ret = -ENODEV;
+		goto err;
+	}
+
+	wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
+	if (!wcd937x->tx_swr_dev) {
+		dev_err(dev, "%s: Could not find TX swr slave device\n",
+			__func__);
+		ret = -ENODEV;
+		goto err;
+	}
+
+	wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
+					       &wcd937x_regmap_config);
+	if (!wcd937x->regmap) {
+		dev_err(dev, "%s: Regmap init failed\n",
+				__func__);
+		goto err;
+	}
+
+	ret = snd_soc_register_codec(dev, &soc_codec_dev_wcd937x,
+				     NULL, 0);
+	if (ret) {
+		dev_err(dev, "%s: Codec registration failed\n",
+				__func__);
+		goto err;
+	}
+
+	return ret;
+err:
+	component_unbind_all(dev, wcd937x);
+	return ret;
+}
+
+static void wcd937x_unbind(struct device *dev)
+{
+	struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
+
+	snd_soc_unregister_codec(dev);
+	component_unbind_all(dev, wcd937x);
+}
+
+static const struct of_device_id wcd937x_dt_match[] = {
+	{ .compatible = "qcom,wcd937x-codec" },
+	{}
+};
+
+static const struct component_master_ops wcd937x_comp_ops = {
+	.bind   = wcd937x_bind,
+	.unbind = wcd937x_unbind,
+};
+
+static int wcd937x_compare_of(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+static void wcd937x_release_of(struct device *dev, void *data)
+{
+	of_node_put(data);
+}
+
+static int wcd937x_add_slave_components(struct device *dev,
+				struct component_match **matchptr)
+{
+	struct device_node *np, *rx_node, *tx_node;
+
+	np = dev->of_node;
+
+	rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
+	if (!rx_node) {
+		dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
+		return -ENODEV;
+	}
+	of_node_get(rx_node);
+	component_match_add_release(dev, matchptr,
+			wcd937x_release_of,
+			wcd937x_compare_of,
+			rx_node);
+
+	tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
+	if (!tx_node) {
+		dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
+			return -ENODEV;
+	}
+	of_node_get(tx_node);
+	component_match_add_release(dev, matchptr,
+			wcd937x_release_of,
+			wcd937x_compare_of,
+			tx_node);
+	return 0;
+}
+
+static int wcd937x_probe(struct platform_device *pdev)
+{
+	struct component_match *match = NULL;
+	int ret;
+
+	ret = wcd937x_add_slave_components(&pdev->dev, &match);
+	if (ret)
+		return ret;
+
+	return component_master_add_with_match(&pdev->dev,
+					&wcd937x_comp_ops, match);
+}
+
+static int wcd937x_remove(struct platform_device *pdev)
+{
+	component_master_del(&pdev->dev, &wcd937x_comp_ops);
+	return 0;
+}
+
+static struct platform_driver wcd937x_codec_driver = {
+	.probe = wcd937x_probe,
+	.remove = wcd937x_remove,
+	.driver = {
+		.name = "wcd937x_codec",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wcd937x_dt_match),
+	},
+};
+
+module_platform_driver(wcd937x_codec_driver);
+MODULE_DESCRIPTION("WCD937X Codec driver");
+MODULE_LICENSE("GPL v2");

+ 124 - 0
asoc/codecs/wcd937x/wcd937x_slave.c

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/component.h>
+#include <soc/soundwire.h>
+
+struct wcd937x_slave_priv {
+	struct swr_device *swr_slave;
+};
+
+static int wcd937x_slave_bind(struct device *dev,
+				struct device *master, void *data)
+{
+	int ret = 0;
+	struct wcd937x_slave_priv *wcd937x_slave = NULL;
+	uint8_t devnum = 0;
+	struct swr_device *pdev = to_swr_device(dev);
+
+	wcd937x_slave = devm_kzalloc(&pdev->dev,
+				sizeof(struct wcd937x_slave_priv), GFP_KERNEL);
+	if (!wcd937x_slave)
+		return -ENOMEM;
+
+	swr_set_dev_data(pdev, wcd937x_slave);
+
+	wcd937x_slave->swr_slave = pdev;
+
+	ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
+	if (ret) {
+		dev_dbg(&pdev->dev,
+				"%s get devnum %d for dev addr %lx failed\n",
+				__func__, devnum, pdev->addr);
+		swr_remove_device(pdev);
+		return ret;
+	}
+	pdev->dev_num = devnum;
+
+	return ret;
+}
+
+static void wcd937x_slave_unbind(struct device *dev,
+				struct device *master, void *data)
+{
+	struct wcd937x_slave_priv *wcd937x_slave = NULL;
+	struct swr_device *pdev = to_swr_device(dev);
+
+	wcd937x_slave = swr_get_dev_data(pdev);
+	if (!wcd937x_slave) {
+		dev_err(&pdev->dev, "%s: wcd937x_slave is NULL\n", __func__);
+		return;
+	}
+
+	swr_set_dev_data(pdev, NULL);
+}
+
+static const struct swr_device_id wcd937x_swr_id[] = {
+	{"wcd937x-slave", 0},
+	{}
+};
+
+static const struct of_device_id wcd937x_swr_dt_match[] = {
+	{
+		.compatible = "qcom,wcd937x-slave",
+	},
+	{}
+};
+
+static const struct component_ops wcd937x_slave_comp_ops = {
+	.bind   = wcd937x_slave_bind,
+	.unbind = wcd937x_slave_unbind,
+};
+
+static int wcd937x_swr_probe(struct swr_device *pdev)
+{
+	return component_add(&pdev->dev, &wcd937x_slave_comp_ops);
+}
+
+static int wcd937x_swr_remove(struct swr_device *pdev)
+{
+	component_del(&pdev->dev, &wcd937x_slave_comp_ops);
+	return 0;
+}
+
+static struct swr_driver wcd937x_slave_driver = {
+	.driver = {
+		.name = "wcd937x-slave",
+		.owner = THIS_MODULE,
+		.of_match_table = wcd937x_swr_dt_match,
+	},
+	.probe = wcd937x_swr_probe,
+	.remove = wcd937x_swr_remove,
+	.id_table = wcd937x_swr_id,
+};
+
+static int __init wcd937x_slave_init(void)
+{
+	return swr_driver_register(&wcd937x_slave_driver);
+}
+
+static void __exit wcd937x_slave_exit(void)
+{
+	swr_driver_unregister(&wcd937x_slave_driver);
+}
+
+module_init(wcd937x_slave_init);
+module_exit(wcd937x_slave_exit);
+
+MODULE_DESCRIPTION("WCD937X Swr Slave driver");
+MODULE_LICENSE("GPL v2");

+ 3 - 0
include/soc/soundwire.h

@@ -335,4 +335,7 @@ extern int swr_slvdev_datapath_control(struct swr_device *swr_dev, u8 dev_num,
 extern int swr_remove_from_group(struct swr_device *dev, u8 dev_num);
 
 extern void swr_remove_device(struct swr_device *swr_dev);
+
+extern struct swr_device *get_matching_swr_slave_device(struct device_node *np);
+
 #endif /* _LINUX_SOUNDWIRE_H */

+ 20 - 0
soc/soundwire.c

@@ -792,6 +792,26 @@ void swr_master_add_boarddevices(struct swr_master *master)
 }
 EXPORT_SYMBOL(swr_master_add_boarddevices);
 
+struct swr_device *get_matching_swr_slave_device(struct device_node *np)
+{
+	struct swr_device *swr = NULL;
+	struct swr_master *master;
+
+	mutex_lock(&board_lock);
+	list_for_each_entry(master, &swr_master_list, list) {
+		mutex_lock(&master->mlock);
+		list_for_each_entry(swr, &master->devices, dev_list) {
+			if (swr->dev.of_node == np)
+				break;
+		}
+		mutex_unlock(&master->mlock);
+	}
+	mutex_unlock(&board_lock);
+
+	return swr;
+}
+EXPORT_SYMBOL(get_matching_swr_slave_device);
+
 static void swr_unregister_device(struct swr_device *swr)
 {
 	if (swr)