diff --git a/msm/sde/sde_hw_reg_dma_v1.c b/msm/sde/sde_hw_reg_dma_v1.c
index e0a5c220a9..78130b6610 100644
--- a/msm/sde/sde_hw_reg_dma_v1.c
+++ b/msm/sde/sde_hw_reg_dma_v1.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -40,7 +41,7 @@
 
 
 #define GRP_VIG_HW_BLK_SELECT (VIG0 | VIG1 | VIG2 | VIG3)
-#define GRP_DMA_HW_BLK_SELECT (DMA0 | DMA1 | DMA2 | DMA3)
+#define GRP_DMA_HW_BLK_SELECT (DMA0 | DMA1 | DMA2 | DMA3 | DMA4 | DMA5)
 #define GRP_DSPP_HW_BLK_SELECT (DSPP0 | DSPP1 | DSPP2 | DSPP3)
 #define GRP_LTM_HW_BLK_SELECT (LTM0 | LTM1)
 #define GRP_MDSS_HW_BLK_SELECT (MDSS)
@@ -210,6 +211,12 @@ static void get_decode_sel(unsigned long blk, u32 *decode_sel)
 		case DMA3:
 			*decode_sel |= BIT(8);
 			break;
+		case DMA4:
+			*decode_sel |= BIT(9);
+			break;
+		case DMA5:
+			*decode_sel |= BIT(10);
+			break;
 		case DSPP0:
 			*decode_sel |= BIT(17);
 			break;
diff --git a/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index 9cde9f51ef..513def741b 100644
--- a/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -209,6 +210,8 @@ static u32 sspp_mapping[SSPP_MAX] = {
 	[SSPP_DMA1] = DMA1,
 	[SSPP_DMA2] = DMA2,
 	[SSPP_DMA3] = DMA3,
+	[SSPP_DMA4] = DMA4,
+	[SSPP_DMA5] = DMA5,
 };
 
 static u32 ltm_mapping[LTM_MAX] = {
diff --git a/msm/sde/sde_reg_dma.h b/msm/sde/sde_reg_dma.h
index 1a5f2b74f0..22ba603616 100644
--- a/msm/sde/sde_reg_dma.h
+++ b/msm/sde/sde_reg_dma.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -180,6 +181,8 @@ enum sde_reg_dma_setup_ops {
  * @DMA1: select dma1 block
  * @DMA2: select dma2 block
  * @DMA3: select dma3 block
+ * @DMA4: select dma4 block
+ * @DMA5: select dma5 block
  * @SSPP_IGC: select sspp igc block
  * @DSPP_IGC: select dspp igc block
  * @LTM0: select LTM0 block
@@ -207,6 +210,8 @@ enum sde_reg_dma_blk {
 	DSPP_IGC = BIT(17),
 	LTM0 = BIT(18),
 	LTM1 = BIT(19),
+	DMA4  = BIT(20),
+	DMA5  = BIT(21),
 	MDSS  = BIT(31)
 };