Merge "disp: msm: dsi: snapshot of dsi from 4.14 to 4.19"
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@@ -78,6 +78,11 @@ static int dsi_display_config_clk_gating(struct dsi_display *display,
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return -EINVAL;
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}
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if (display->panel->host_config.force_hs_clk_lane) {
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pr_debug("no dsi clock gating for continuous clock mode\n");
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return 0;
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}
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mctrl = &display->ctrl[display->clk_master_idx];
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if (!mctrl) {
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pr_err("Invalid controller\n");
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@@ -586,8 +591,11 @@ static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
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for (j = 0; j < config->groups; ++j) {
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for (i = 0; i < len; ++i) {
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if (config->return_buf[i] !=
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config->status_value[group + i])
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config->status_value[group + i]) {
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DRM_ERROR("mismatch: 0x%x\n",
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config->return_buf[i]);
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break;
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}
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}
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if (i == len)
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@@ -828,6 +836,11 @@ int dsi_display_check_status(struct drm_connector *connector, void *display,
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if (te_check_override && gpio_is_valid(dsi_display->disp_te_gpio))
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status_mode = ESD_MODE_PANEL_TE;
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if (status_mode == ESD_MODE_PANEL_TE) {
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rc = dsi_display_status_check_te(dsi_display);
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goto exit;
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}
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dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
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DSI_ALL_CLKS, DSI_CLK_ON);
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@@ -843,23 +856,25 @@ int dsi_display_check_status(struct drm_connector *connector, void *display,
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} else if (status_mode == ESD_MODE_PANEL_TE) {
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rc = dsi_display_status_check_te(dsi_display);
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} else {
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pr_warn("unsupported check status mode\n");
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pr_warn("Unsupported check status mode: %d\n", status_mode);
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panel->esd_config.esd_enabled = false;
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}
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/* Unmask error interrupts */
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/* Unmask error interrupts if check passed*/
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if (rc > 0) {
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dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
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dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
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false);
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} else {
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/* Handle Panel failures during display disable sequence */
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atomic_set(&panel->esd_recovery_pending, 1);
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}
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dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
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DSI_ALL_CLKS, DSI_CLK_OFF);
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exit:
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/* Handle Panel failures during display disable sequence */
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if (rc <=0)
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atomic_set(&panel->esd_recovery_pending, 1);
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release_panel_lock:
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dsi_panel_release_panel_lock(panel);
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SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
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@@ -1620,12 +1635,25 @@ static int dsi_display_debugfs_deinit(struct dsi_display *display)
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static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
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struct dsi_display_mode *mode)
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{
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mode->timing.h_active /= display->ctrl_count;
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mode->timing.h_front_porch /= display->ctrl_count;
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mode->timing.h_sync_width /= display->ctrl_count;
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mode->timing.h_back_porch /= display->ctrl_count;
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mode->timing.h_skew /= display->ctrl_count;
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mode->pixel_clk_khz /= display->ctrl_count;
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struct dsi_host_common_cfg *host = &display->panel->host_config;
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bool is_split_link = host->split_link.split_link_enabled;
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u32 sublinks_count = host->split_link.num_sublinks;
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if (is_split_link && sublinks_count > 1) {
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mode->timing.h_active /= sublinks_count;
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mode->timing.h_front_porch /= sublinks_count;
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mode->timing.h_sync_width /= sublinks_count;
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mode->timing.h_back_porch /= sublinks_count;
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mode->timing.h_skew /= sublinks_count;
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mode->pixel_clk_khz /= sublinks_count;
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} else {
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mode->timing.h_active /= display->ctrl_count;
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mode->timing.h_front_porch /= display->ctrl_count;
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mode->timing.h_sync_width /= display->ctrl_count;
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mode->timing.h_back_porch /= display->ctrl_count;
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mode->timing.h_skew /= display->ctrl_count;
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mode->pixel_clk_khz /= display->ctrl_count;
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}
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}
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static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
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@@ -2366,7 +2394,9 @@ static int dsi_display_ctrl_init(struct dsi_display *display)
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} else {
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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rc = dsi_ctrl_update_host_init_state(ctrl->ctrl, true);
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rc = dsi_ctrl_update_host_state(ctrl->ctrl,
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DSI_CTRL_OP_HOST_INIT,
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true);
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if (rc)
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pr_debug("host init update failed rc=%d\n", rc);
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}
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@@ -2450,6 +2480,25 @@ static int dsi_display_ctrl_host_disable(struct dsi_display *display)
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struct dsi_display_ctrl *m_ctrl, *ctrl;
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m_ctrl = &display->ctrl[display->cmd_master_idx];
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/*
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* For platforms where ULPS is controlled by DSI controller block,
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* do not disable dsi controller block if lanes are to be
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* kept in ULPS during suspend. So just update the SW state
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* and return early.
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*/
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if (display->panel->ulps_suspend_enabled &&
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!m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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rc = dsi_ctrl_update_host_state(ctrl->ctrl,
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DSI_CTRL_OP_HOST_ENGINE,
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false);
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if (rc)
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pr_debug("host state update failed %d\n", rc);
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}
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return rc;
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}
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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if (!ctrl->ctrl || (ctrl == m_ctrl))
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@@ -4609,6 +4658,42 @@ static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
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return rc;
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}
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static int dsi_display_validate_split_link(struct dsi_display *display)
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{
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int i, rc = 0;
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struct dsi_display_ctrl *ctrl;
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struct dsi_host_common_cfg *host = &display->panel->host_config;
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if (!host->split_link.split_link_enabled)
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return 0;
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if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
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pr_err("[%s] split link is not supported in command mode\n",
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display->name);
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rc = -ENOTSUPP;
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goto error;
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}
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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if (!ctrl->ctrl->split_link_supported) {
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pr_err("[%s] split link is not supported by hw\n",
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display->name);
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rc = -ENOTSUPP;
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goto error;
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}
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set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
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}
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pr_debug("Split link is enabled\n");
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return 0;
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error:
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host->split_link.split_link_enabled = false;
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return rc;
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}
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/**
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* dsi_display_bind - bind dsi device with controlling device
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* @dev: Pointer to base of platform device
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@@ -4649,8 +4734,28 @@ static int dsi_display_bind(struct device *dev,
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if (!display->fw)
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display->name = display->panel_node->name;
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/* defer bind if ext bridge driver is not loaded */
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if (display->panel && display->panel->host_config.ext_bridge_mode) {
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for (i = 0; i < display->ext_bridge_cnt; i++) {
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if (!of_drm_find_bridge(
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display->ext_bridge[i].node_of)) {
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pr_debug("defer for bridge[%d] %s\n", i,
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display->ext_bridge[i].node_of->full_name);
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return -EPROBE_DEFER;
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}
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}
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}
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mutex_lock(&display->display_lock);
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rc = dsi_display_validate_split_link(display);
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if (rc) {
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pr_err("[%s] split link validation failed, rc=%d\n",
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display->name, rc);
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goto error;
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}
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rc = dsi_display_debugfs_init(display);
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if (rc) {
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pr_err("[%s] debugfs init failed, rc=%d\n", display->name, rc);
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@@ -5276,7 +5381,7 @@ static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
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sde_conn = to_sde_connector(conn_iter);
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if (sde_conn->encoder == bridge->encoder) {
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display = sde_conn->display;
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for (i = 0; i < display->ctrl_count; i++) {
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display_for_each_ctrl(i, display) {
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if (display->ext_bridge[i].bridge == bridge)
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return &display->ext_bridge[i];
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}
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@@ -5443,6 +5548,9 @@ int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
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struct drm_bridge *prev_bridge = bridge;
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int rc = 0, i;
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if (display->panel && !display->panel->host_config.ext_bridge_mode)
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return 0;
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for (i = 0; i < display->ext_bridge_cnt; i++) {
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struct dsi_display_ext_bridge *ext_bridge_info =
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&display->ext_bridge[i];
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@@ -5753,8 +5861,10 @@ int dsi_display_get_modes(struct dsi_display *display,
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{
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struct dsi_dfps_capabilities dfps_caps;
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struct dsi_display_ctrl *ctrl;
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struct dsi_host_common_cfg *host = &display->panel->host_config;
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bool is_split_link;
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u32 num_dfps_rates, panel_mode_count, total_mode_count;
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u32 mode_idx, array_idx = 0;
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u32 sublinks_count, mode_idx, array_idx = 0;
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struct dsi_dyn_clk_caps *dyn_clk_caps;
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int i, start, end, rc = -EINVAL;
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@@ -5830,15 +5940,25 @@ int dsi_display_get_modes(struct dsi_display *display,
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panel_mode.timing.dsi_transfer_time_us;
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}
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panel_mode.timing.h_active *= display->ctrl_count;
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panel_mode.timing.h_front_porch *= display->ctrl_count;
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panel_mode.timing.h_sync_width *= display->ctrl_count;
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panel_mode.timing.h_back_porch *= display->ctrl_count;
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panel_mode.timing.h_skew *= display->ctrl_count;
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panel_mode.pixel_clk_khz *= display->ctrl_count;
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is_split_link = host->split_link.split_link_enabled;
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sublinks_count = host->split_link.num_sublinks;
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if (is_split_link && sublinks_count > 1) {
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panel_mode.timing.h_active *= sublinks_count;
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panel_mode.timing.h_front_porch *= sublinks_count;
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panel_mode.timing.h_sync_width *= sublinks_count;
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panel_mode.timing.h_back_porch *= sublinks_count;
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panel_mode.timing.h_skew *= sublinks_count;
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panel_mode.pixel_clk_khz *= sublinks_count;
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} else {
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panel_mode.timing.h_active *= display->ctrl_count;
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panel_mode.timing.h_front_porch *= display->ctrl_count;
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panel_mode.timing.h_sync_width *= display->ctrl_count;
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panel_mode.timing.h_back_porch *= display->ctrl_count;
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panel_mode.timing.h_skew *= display->ctrl_count;
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panel_mode.pixel_clk_khz *= display->ctrl_count;
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}
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start = array_idx;
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for (i = 0; i < num_dfps_rates; i++) {
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struct dsi_display_mode *sub_mode =
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&display->modes[array_idx];
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@@ -5889,6 +6009,7 @@ int dsi_display_get_panel_vfp(void *dsi_display,
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u32 count, refresh_rate = 0;
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struct dsi_dfps_capabilities dfps_caps;
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struct dsi_display *display = (struct dsi_display *)dsi_display;
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struct dsi_host_common_cfg *host;
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if (!display)
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return -EINVAL;
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@@ -5912,7 +6033,11 @@ int dsi_display_get_panel_vfp(void *dsi_display,
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return -EINVAL;
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}
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h_active *= display->ctrl_count;
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host = &display->panel->host_config;
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if (host->split_link.split_link_enabled)
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h_active *= host->split_link.num_sublinks;
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else
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h_active *= display->ctrl_count;
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for (i = 0; i < count; i++) {
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struct dsi_display_mode *m = &display->modes[i];
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@@ -6577,7 +6702,8 @@ int dsi_display_prepare(struct dsi_display *display)
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if (display->is_cont_splash_enabled &&
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display->config.panel_mode == DSI_OP_VIDEO_MODE) {
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pr_err("DMS not supported on first frame\n");
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return -EINVAL;
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rc = -EINVAL;
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goto error;
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}
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/* update dsi ctrl for new mode */
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@@ -6774,8 +6900,7 @@ static int dsi_display_qsync(struct dsi_display *display, bool enable)
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mutex_lock(&display->display_lock);
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for (i = 0; i < display->ctrl_count; i++) {
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display_for_each_ctrl(i, display) {
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if (enable) {
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/* send the commands to enable qsync */
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rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
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