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qcacmn: Add hal_rx_msdu_flow_idx_timeout API

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Implement hal_rx_msdu_flow_idx_timeout API
per chipset as the macro
to retrieve the flow_idx_timeout value is
chipset dependent.

Change-Id: I03030e3763b3c4a9099699a2d24b8110961610cf
CRs-Fixed: 2522133
This commit is contained in:
Venkata Sharath Chandra Manchala
2019-09-25 12:07:09 -07:00
committed by nshrivas
parent b9a8536661
commit b5ec9d28ee
13 changed files with 132 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
hal/wifi3.0/hal_internal.h
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@@ -439,6 +439,7 @@ struct hal_hw_txrx_ops {
struct hal_reo_params *reo_params); struct hal_reo_params *reo_params);
uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
}; };
/** /**

17
hal/wifi3.0/hal_rx.h
View File

@@ -3219,12 +3219,6 @@ hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf);
} }
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
/** /**
* hal_rx_msdu_flow_idx_timeout: API to get flow index timeout * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout
* from rx_msdu_end TLV * from rx_msdu_end TLV
@@ -3232,14 +3226,13 @@ hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
* *
* Return: flow index timeout value from MSDU END TLV * Return: flow index timeout value from MSDU END TLV
*/ */
static inline bool hal_rx_msdu_flow_idx_timeout(uint8_t *buf) static inline bool
hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf)
{ {
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
bool timeout;
timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf);
return timeout;
} }
/** /**

16
hal/wifi3.0/qca6290/hal_6290.c
View File

@@ -880,6 +880,21 @@ static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf)
return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
} }
/**
* hal_rx_msdu_flow_idx_timeout_6290: API to get flow index timeout
* from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: flow index timeout value from MSDU END TLV
*/
static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
}
struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
hal_srng_dst_hw_init_generic, hal_srng_dst_hw_init_generic,
@@ -959,6 +974,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
hal_reo_config_6290, hal_reo_config_6290,
hal_rx_msdu_flow_idx_get_6290, hal_rx_msdu_flow_idx_get_6290,
hal_rx_msdu_flow_idx_invalid_6290, hal_rx_msdu_flow_idx_invalid_6290,
hal_rx_msdu_flow_idx_timeout_6290,
}; };
struct hal_hw_srng_config hw_srng_table_6290[] = { struct hal_hw_srng_config hw_srng_table_6290[] = {

6
hal/wifi3.0/qca6290/hal_6290_rx.h
View File

@@ -306,6 +306,12 @@ UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
#if defined(QCA_WIFI_QCA6290_11AX) #if defined(QCA_WIFI_QCA6290_11AX)
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\

16
hal/wifi3.0/qca6390/hal_6390.c
View File

@@ -876,6 +876,21 @@ static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf)
return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
} }
/**
* hal_rx_msdu_flow_idx_timeout_6390: API to get flow index timeout
* from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: flow index timeout value from MSDU END TLV
*/
static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
}
struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
hal_srng_dst_hw_init_generic, hal_srng_dst_hw_init_generic,
@@ -955,6 +970,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
hal_reo_config_6390, hal_reo_config_6390,
hal_rx_msdu_flow_idx_get_6390, hal_rx_msdu_flow_idx_get_6390,
hal_rx_msdu_flow_idx_invalid_6390, hal_rx_msdu_flow_idx_invalid_6390,
hal_rx_msdu_flow_idx_timeout_6390,
}; };
struct hal_hw_srng_config hw_srng_table_6390[] = { struct hal_hw_srng_config hw_srng_table_6390[] = {

6
hal/wifi3.0/qca6390/hal_6390_rx.h
View File

@@ -311,6 +311,12 @@ UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \
RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
/* /*
* hal_rx_msdu_start_nss_get_6390(): API to get the NSS * hal_rx_msdu_start_nss_get_6390(): API to get the NSS
* Interval from rx_msdu_start * Interval from rx_msdu_start

16
hal/wifi3.0/qca6490/hal_6490.c
View File

@@ -750,6 +750,21 @@ static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf)
return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
} }
/**
* hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout
* from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: flow index timeout value from MSDU END TLV
*/
static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
}
struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
/* tx */ /* tx */
hal_tx_desc_set_mesh_en_6490, hal_tx_desc_set_mesh_en_6490,
@@ -791,4 +806,5 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
hal_reo_config_6490, hal_reo_config_6490,
hal_rx_msdu_flow_idx_get_6490, hal_rx_msdu_flow_idx_get_6490,
hal_rx_msdu_flow_idx_invalid_6490, hal_rx_msdu_flow_idx_invalid_6490,
hal_rx_msdu_flow_idx_timeout_6490,
}; };

6
hal/wifi3.0/qca6490/hal_6490_rx.h
View File

@@ -296,3 +296,9 @@ RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \
RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \
RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) RX_MSDU_END_10_FLOW_IDX_INVALID_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB))

16
hal/wifi3.0/qca8074v1/hal_8074v1.c
View File

@@ -876,6 +876,21 @@ static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf)
return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
} }
/**
* hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout
* from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: flow index timeout value from MSDU END TLV
*/
static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
}
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -956,6 +971,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
hal_reo_config_8074v1, hal_reo_config_8074v1,
hal_rx_msdu_flow_idx_get_8074v1, hal_rx_msdu_flow_idx_get_8074v1,
hal_rx_msdu_flow_idx_invalid_8074v1, hal_rx_msdu_flow_idx_invalid_8074v1,
hal_rx_msdu_flow_idx_timeout_8074v1,
}; };
struct hal_hw_srng_config hw_srng_table_8074[] = { struct hal_hw_srng_config hw_srng_table_8074[] = {

6
hal/wifi3.0/qca8074v1/hal_8074v1_rx.h
View File

@@ -295,6 +295,12 @@ UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
/* /*
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS * hal_rx_msdu_start_nss_get_8074(): API to get the NSS
* Interval from rx_msdu_start * Interval from rx_msdu_start

16
hal/wifi3.0/qca8074v2/hal_8074v2.c
View File

@@ -873,6 +873,21 @@ static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf)
return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
} }
/**
* hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout
* from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: flow index timeout value from MSDU END TLV
*/
static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
}
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -954,6 +969,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
hal_reo_config_8074v2, hal_reo_config_8074v2,
hal_rx_msdu_flow_idx_get_8074v2, hal_rx_msdu_flow_idx_get_8074v2,
hal_rx_msdu_flow_idx_invalid_8074v2, hal_rx_msdu_flow_idx_invalid_8074v2,
hal_rx_msdu_flow_idx_timeout_8074v2,
}; };
struct hal_hw_srng_config hw_srng_table_8074v2[] = { struct hal_hw_srng_config hw_srng_table_8074v2[] = {

6
hal/wifi3.0/qca8074v2/hal_8074v2_rx.h
View File

@@ -304,6 +304,12 @@ UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
/* /*
* hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
* Interval from rx_msdu_start * Interval from rx_msdu_start

16
hal/wifi3.0/qcn9000/hal_9000.c
View File

@@ -882,6 +882,21 @@ static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf)
return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
} }
/**
* hal_rx_msdu_flow_idx_timeout_9000: API to get flow index timeout
* from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: flow index timeout value from MSDU END TLV
*/
static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
}
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -963,6 +978,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
hal_reo_config_9000, hal_reo_config_9000,
hal_rx_msdu_flow_idx_get_9000, hal_rx_msdu_flow_idx_get_9000,
hal_rx_msdu_flow_idx_invalid_9000, hal_rx_msdu_flow_idx_invalid_9000,
hal_rx_msdu_flow_idx_timeout_9000,
}; };
struct hal_hw_srng_config hw_srng_table_9000[] = { struct hal_hw_srng_config hw_srng_table_9000[] = {